USRE45418EActiveUtility

Reconfigurable tunable RF power amplifier

38
Assignee: DAWE GEOFFREY CPriority: May 24, 2007Filed: Jul 27, 2012Granted: Mar 17, 2015
Est. expiryMay 24, 2027(~0.9 yrs left)· nominal 20-yr term from priority
Inventors:Geoffrey C. Dawe
H03F 2200/222H03F 2200/421H03H 7/38H03F 1/56H03F 3/1935H03F 2200/451H03F 2200/252H03F 2200/366H03F 2200/387H03G 1/0088H03F 2200/75H03F 2200/393H03F 3/72H03G 3/3042H03F 2203/7209H03F 2203/7236H03F 3/193H03F 2200/111H03H 2007/386H03F 2200/492
38
PatentIndex Score
0
Cited by
28
References
32
Claims

Abstract

A multi-band, multi-standard programmable power amplifier having tunable impedance matching input and output networks and programmable device characteristics. The impedance of either or both of the impedance matching input and output networks is tunable responsive to one or more control signals. In one example, the programmable power amplifier incorporates a feedback control loop and the control signal(s) are varied responsive to the feedback loop.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A programmable power amplifier comprising:
 an amplifier comprising a power transistor; 
 an impedance matching input circuit coupled to an input of the amplifier; and 
 an impedance matching output network coupled to an output of the amplifier, the impedance matching output network having a programmable impedance that is adjustable responsive to an impedance control signal; 
 wherein the power transistor comprises a programmable bias circuit including a parallel resonance circuit comprising an inductor and a bank of switchable capacitors that are switched into and out of the bias circuit responsive to a bias control signal. 
 
     
     
       2. The programmable power amplifier as claimed in  claim 1 , wherein the impedance matching output network comprises a plurality of impedance elements including at least one programmable impedance element that is programmable responsive to the impedance control signal. 
     
     
       3. The programmable power amplifier as claimed in  claim 2 , wherein the at least one programmable impedance element includes a bank of switchable capacitors. 
     
     
       4. The programmable power amplifier as claimed in  claim 2 , wherein the at least one programmable impedance element includes a varactor. 
     
     
       5. The programmable power amplifier as claimed in  claim 1 , wherein the impedance matching input circuit comprises at least one programmable impedance element that is programmable responsive to a second impedance control signal. 
     
     
       6. The programmable power amplifier circuit as claimed in  claim 1 , wherein the parallel resonance circuit further comprises a varactor. 
     
     
       7. A programmable power amplifier, comprising:
 an amplifier comprising a power transistor; 
 an impedance matching input circuit coupled to an input of the amplifier; and 
 an impedance matching output network coupled to an output of the amplifier, the impedance matching output network having a programmable impedance that is adjustable responsive to an impedance control signal; 
 wherein the power transistor has a variable gate width, and wherein the variable gate width is programmable responsive to a transistor control signal. 
 
     
     
       8. A digital programmable power amplifier comprising:
 an amplifier stage; 
 a programmable impedance matching input circuit coupled to an input of the amplifier stage; 
 a programmable impedance matching output network coupled to an output of the amplifier stage; 
 an error generator coupled to an output of the programmable impedance matching output network and configured to compare a signal received from the programmable impedance matching output network with a reference signal to generate an error signal; 
 a control circuit coupled to the error generator and configured to receive the error signal; and 
 a digital programming bus coupled to the control circuit and to each of the amplifier stage, the programmable impedance matching input network and the programmable impedance matching output network; 
 wherein the control circuit is configured to generate at least one digital control signal responsive to the error signal and to provide the at least one digital control signal to the amplifier, the programmable impedance matching input network and the programmable impedance matching output network via the digital programming bus; and 
 wherein parameters of the amplifier, the programmable impedance matching input network and the programmable impedance matching output network are variable responsive to the at least one digital control signal. 
 
     
     
       9. The digital programmable power amplifier as claimed in  claim 8 , wherein the parameters that are variable responsive to the at least one digital control signal include an impedance of the impedance matching output network. 
     
     
       10. The digital programmable power amplifier as claimed in  claim 8 , wherein the parameters that are variable responsive to the at least one digital control signal include an impedance of the impedance matching input network. 
     
     
       11. The digital programmable power amplifier as claimed in  claim 8 , wherein the parameters that are variable responsive to the at least one digital control signal include a device width of the amplifier. 
     
     
       12. The digital programmable power amplifier as claimed in  claim 11 , wherein the amplifier includes a FET transistor, and wherein the parameters that are variable responsive to the at least one digital control signal include the gate width of the FET transistor. 
     
     
       13. A method of tuning an operating frequency of a power amplifier that includes a power transistor and an programmable impedance matching output network, the method comprising:
 comparing at least a portion of an output signal from the power amplifier with a reference signal to generate an error signal; 
 generating a control signal responsive to the error signal; 
 varying an impedance of the programmable impedance matching output network of the power amplifier responsive to the control signal; 
 varying a gate width of the power transistor responsive to a transistor control signal. 
 
     
     
       14. A programmable power amplifier comprising:
 a power transistor having a gate width that is adjustable responsive to a transistor control signal;   an error detector configured to generate a control signal based on a comparison of an output signal from an impedance matching output network with a reference signal; and   a control circuit configured to vary an impedance of the impedance matching output network based on the control signal.   
     
     
       15. The programmable power amplifier of claim 14, further comprising an impedance matching input circuit coupled to an input of the amplifier. 
     
     
       16. The programmable power amplifier of claim 15, further comprising an impedance matching output network coupled to an output of the amplifier, the impedance matching output network having a programmable impedance that is adjustable responsive to an impedance control signal. 
     
     
       17. The programmable power amplifier of claim 16, wherein the impedance matching output network comprises a plurality of impedance elements including at least one programmable impedance element that is programmable responsive to the impedance control signal. 
     
     
       18. The programmable power amplifier of claim 17, wherein the at least one programmable impedance element includes a bank of switchable capacitors. 
     
     
       19. The programmable power amplifier of claim 17, wherein the at least one programmable impedance element includes a varactor. 
     
     
       20. The programmable power amplifier of claim 16, wherein the impedance matching input circuit comprises at least one programmable impedance element that is programmable responsive to a second impedance control signal. 
     
     
       21. The programmable power amplifier circuit of claim 14, wherein the parallel resonance circuit further comprises a varactor. 
     
     
       22. A programmable power amplifier, comprising:
 an amplifier comprising a power transistor and a programmable impedance matching output network,   wherein the power transistor comprises a variable gate width, and wherein the variable gate width is programmable responsive to a transistor control signal, and   wherein an impedance of the programmable impedance matching output network is adjustable responsive to a control signal generated based on a comparison of an output of the impedance matching output network with a reference signal.   
     
     
       23. The programmable power amplifier of claim 22, further comprising an impedance matching input circuit coupled to an input of the amplifier. 
     
     
       24. The programmable power amplifier of claim 22, wherein the programmable impedance matching output network is coupled to an output of the amplifier. 
     
     
       25. A digital programmable power amplifier, comprising:
 a programmable impedance matching input network coupled to an input of an amplifier; and   a control circuit configured to receive an error signal based on a comparison of a signal received from a programmable impedance matching output network with a reference signal,   wherein the control circuit is configured to generate at least one digital control signal responsive to the error signal and to provide the at least one digital control signal to the amplifier, the programmable impedance matching input network, and the programmable impedance matching output network; and   wherein respective parameters of the amplifier, the programmable impedance matching input network, and the programmable impedance matching output network are variable responsive to the at least one digital control signal.   
     
     
       26. The digital programmable power amplifier of claim 25, further comprising:
 an amplifier stage;   an error generator coupled to an output of the programmable impedance matching output network and configured to compare a signal received from the programmable impedance matching output network with a reference signal to generate the error signal; and   a digital programming bus coupled to the control circuit and to the amplifier stage, the programmable impedance matching input network, and the programmable impedance matching output network,   wherein the programmable impedance matching output network is coupled to an output of the amplifier stage.   
     
     
       27. The digital programmable power amplifier of claim 25, wherein the parameters that are variable responsive to the at least one digital control signal include an impedance of the programmable impedance matching output network. 
     
     
       28. The digital programmable power amplifier of claim 25, wherein the parameters that are variable responsive to the at least one digital control signal include an impedance of the programmable impedance matching input network. 
     
     
       29. The digital programmable power amplifier of claim 25, wherein the parameters that are variable responsive to the at least one digital control signal include a device width of the amplifier. 
     
     
       30. The digital programmable power amplifier of claim 25, wherein the amplifier includes a field-effect transistor, and wherein the parameters that are variable responsive to the at least one digital control signal include a gate width of the field-effect transistor. 
     
     
       31. A method, comprising:
 generating an error signal based on a comparison of an output signal from an impedance matching output network of a power amplifier with a reference signal;   varying, responsive to the error signal, an impedance of the impedance matching output network of the power amplifier; and   varying, responsive to a transistor control signal, a gate width of a power transistor of the power amplifier.   
     
     
       32. A system, comprising:
 means for generating an error signal in connection with varying an impedance of a programmable impedance matching output network of a power amplifier;   means for varying an impedance of the programmable impedance matching output network in accordance with a control signal responsive to the error signal; and   means for varying a gate width of a power transistor in accordance with a transistor control signal.

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