Semiconductor device

Abstract

A semiconductor device includes a first pMISFET region having an Si channel, a second pMISFET region having an Si channel and an nMISFET region having an Si channel. First SiGe layers which apply first compression strain to the Si channel are embedded and formed in the first pMISFET region to sandwich the Si channel thereof and second SiGe layers which apply second compression strain different from the first compression strain to the Si channel are embedded and formed in the second pMISFET region to sandwich the Si channel thereof.

What is claimed is: 
     
       1. A semiconductor device comprising:
 a semiconductor substrate, 
 a first pMISFET formed on the semiconductor substrate and having a first Si channel formed on a surface of the semiconductor substrate, and first SiGe layers, which apply first compression strain to the first Si channel, embedded in the surface of the semiconductor substrate to sandwich the first Si channel, 
 a second pMISFET formed on the semiconductor substrate to be electrically isolated from the first pMISFET and having a second Si channel formed on a surface of the semiconductor substrate, and second SiGe layers, which apply second compression strain different from the first compression strain to the second Si channel, embedded in the surface of the semiconductor substrate to sandwich the second Si channel, and 
 an nMISFET formed on the semiconductor substrate to be electrically isolated from the first pMISFET and the second pMISFET and having a third Si channel formed on a surface of the semiconductor substrate. 
 
     
     
       2. The semiconductor device according to  claim 1 , wherein the first and second SiGe layers respectively contain B or C as an impurity. 
     
     
       3. The semiconductor device according to  claim 1 , wherein Ge concentrations of the first and second SiGe layers are different. 
     
     
       4. The semiconductor device according to  claim 1 , wherein depths of the first and second SiGe layers from the surface of the substrate are different. 
     
     
       5. The semiconductor device according to  claim 1 , wherein Si aperture ratios of the first pMISFET and the second pMISFET are different in a case where a ratio of an area of an exposed Si substrate to an area of 1 mm 2  including one cell region containing one MISFET therein and an element isolation region surrounding the MISFET is defined as an Si aperture ratio. 
     
     
       6. A semiconductor device comprising:
 a semiconductor layer,   a first pMISFET formed on the semiconductor layer and having a first channel formed on a surface of the semiconductor layer, first SiGe layers, which apply first compression strain to the first channel, embedded in the surface of the semiconductor layer to sandwich the first channel,   a second pMISFET formed on the semiconductor layer to be electrically isolated from the first pMISFET and having a second channel formed on a surface of the semiconductor layer, second SiGe layers, which apply second compression strain different from the first compression strain to the second channel, embedded in the surface of the semiconductor layer to sandwich the second channel, and   an nMISFET formed on the semiconductor layer to be electrically isolated from the first pMISFET and the second pMISFET and having a third channel formed on a surface of the semiconductor layer.   
     
     
       7. The semiconductor device according to claim 6, wherein the first and second SiGe layers respectively contain B or C as an impurity. 
     
     
       8. The semiconductor device according to claim 6, wherein Ge concentrations of the first and second SiGe layers are different. 
     
     
       9. The semiconductor device according to claim 6, wherein depths of the first and second SiGe layers from the surface of the semiconductor layer are different. 
     
     
       10. The semiconductor device according to claim 6, wherein semiconductor-layer aperture ratios of the first pMISFET and the second pMISFET are different in a case where a ratio of an area of an exposed semiconductor layer to an area of 1 mm 2  containing one MISFET and an element isolation region surrounding the MISFET is defined as a semiconductor-layer aperture ratio. 
     
     
       11. The semiconductor device according to claim 10, wherein the first pMISFET is different from the second pMISFET in a length in a gate-length direction between an inner edge of the element isolation region and an opposite inner edge of the element isolation region which is surrounding the MISFET. 
     
     
       12. The semiconductor device according to claim 10, wherein the first pMISFET is different from the second pMISFET in a length in a gate-width direction between an inner edge of the element isolation region and an opposite inner edge of the element isolation region which is surrounding the MISFET. 
     
     
       13. The semiconductor device according to claim 6, wherein the first SiGe layers are different from the second SiGe layers in an impurity concentration and a thickness regarding each of the first and second SiGe layers. 
     
     
       14. The semiconductor device according to claim 10, wherein mobility of the first pMISFET is higher than that of the second pMISFET.