Nonvolatile semiconductor memory device and producing method thereof

Abstract

A cell array includes a memory cell region in which memory cells are formed and a peripheral region that is provided around the memory cell region. In the memory cell region, first lines are extended in parallel with a first direction, and the first lines are repeatedly formed at first intervals in a second direction orthogonal to the first direction. In the peripheral region, each of the first lines located at (4n−3)-th (n is a positive integer) and (4n−2)-th positions in the second direction from a predetermined position has a contact connecting portion on one end side in the first direction of the first line. In the peripheral region, each of the first lines located at (4n−1)-th and 4n-th positions in the second direction from the predetermined position has the contact connecting portion on the other end side in the first direction of the first line. The contact connecting portion is formed so as to contact a contact plug extended in a laminating direction.

What is claimed is: 
     
       1. A nonvolatile semiconductor memory device comprising:
 a semiconductor substrate; and 
 a cell array formed on above the semiconductor substrate, including a plurality of first lines, a plurality of second lines intersecting the plurality of first lines, and a plurality of memory cells connected at intersections of the first and second lines between both lines, 
 wherein the cell array includes: 
 a memory cell region where the memory cells are formed disposed; and 
 a peripheral region that is provided around the memory cell region, 
 in the memory cell region, the first lines are extended in parallel with a first direction, and the first lines are repeatedly formed at first intervals in a second direction orthogonal to the first direction, and the second lines are extended in parallel with the second direction,  
 in the peripheral region, each of the first lines located at (4n−3)-th (n is a positive integer) and (4n−2)-th positions in the second direction from a predetermined position has have a contact connecting portion on one end side in the first direction of the first line, 
 in the peripheral region, each of the first lines located at (4n−1)-th and 4n-th positions in the second direction from the predetermined position has have the contact connecting portion on the other end side in the first direction of the first line, and 
 the contact connecting portion is formed so as to contact with a contact plug extended in a laminating direction orthogonal to both of the first direction and the second direction. 
 
     
     
       2. The nonvolatile semiconductor memory device according to  claim 1 , wherein the first interval is 40 nm or less. 
     
     
       3. The nonvolatile semiconductor memory device according to  claim 1 , wherein the cell array comprises includes:
 a first cell array that is provided at a predetermined position in the laminating direction; and 
 a second cell array that is provided on or beneath the first cell array, and 
 wherein the first line included in the first cell array has a shape identical to that of the first line included in the second cell array. 
 
     
     
       4. The nonvolatile semiconductor memory device according to  claim 1 , wherein the contact connecting portion is formed such that the contact plug contacts an upper surface or a lower surface of the contact connecting portion. 
     
     
       5. The nonvolatile semiconductor memory device according to  claim 1 , wherein the contact connecting portion is formed such that the contact plug contacts a side face of the contact connecting portion. 
     
     
       6. The nonvolatile semiconductor memory device according to  claim 1 , wherein the first line includes an island portion separated from the contact connecting portion, and
 the island portion is formed so as to contact the contact plug. 
 
     
     
       7. The nonvolatile semiconductor memory device according to  claim 1 , wherein the memory cell comprises includes:
 a rectifying element; and 
 a variable resistive element that is connected in series with the rectifying element. 
 
     
     
       8. The nonvolatile semiconductor memory device according to  claim 1 , wherein a first contact plug connected to the contact connecting portion of the first line provided on a predetermined layer and a second contact plug connected to the contact connecting portion of the first line provided on an upper layer of the predetermined layer have same upper end positions and lower end positions in the laminating direction,
 the first contact plug is extended through the layer, in which the contact connecting portion of the first line connected to the second contact plug is formed, to an upper layer with no contact to the contact connecting portion. 
 
     
     
       9. The nonvolatile semiconductor memory device according to  claim 1 , wherein a through-hole is made in the contact connecting portion, and
 the contact plug is formed in the through-hole. 
 
     
     
       10. A nonvolatile semiconductor memory device comprising:
 a semiconductor substrate; and 
 a cell array formed on above the semiconductor substrate, including a plurality of first lines, a plurality of second lines intersecting the plurality of first lines, and a plurality of memory cells connected at intersections of the first and second lines between both lines, 
 wherein the cell array includes: 
 a memory cell region where the memory cells are formed; and 
 a peripheral region that is provided around the memory cell region, 
 in the memory cell region, the first lines are extended in parallel with a first direction, and the first lines are repeatedly formed at first intervals in a second direction orthogonal to the first direction, and the second lines are extended in parallel with the second direction,  
 in the peripheral region, each plurality of continuous first lines alternately have contact connecting portions are disposed on one end side and the other end side in the first direction of the first line, and 
 the contact connecting portion is formed so as to contact with a contact plug extended in a laminating direction orthogonal to both of the first direction and the second direction. 
 
     
     
       11. The nonvolatile semiconductor memory device according to  claim 10 , wherein the first interval is 40 nm or less. 
     
     
       12. The nonvolatile semiconductor memory device according to  claim 10 , wherein the cell array comprises includes:
 a first cell array that is provided at a predetermined position in the laminating direction; and 
 a second cell array that is provided above or beneath the first cell array, and 
 wherein the first line included in the first cell array has a shape identical to that of the first line included in the second cell array. 
 
     
     
       13. The nonvolatile semiconductor memory device according to  claim 10 , wherein the contact connecting portion is formed such that the contact plug contacts a side face of the contact connecting portion. 
     
     
       14. The nonvolatile semiconductor memory device according to  claim 10 , wherein the first line includes an island portion that is disposed while separated from the contact connecting portion, and
 the island portion is formed so as to contact the contact plug. 
 
     
     
       15. The nonvolatile semiconductor memory device according to  claim 10 , wherein the memory cell comprises includes:
 a rectifying element that is connected to the first line; and 
 a variable resistive element that is connected in series with the rectifying element. 
 
     
     
       16. The nonvolatile semiconductor memory device according to  claim 10 , wherein a first contact plug connected to the contact connecting portion of the first line provided on a predetermined layer and a second contact plug connected to the contact connecting portion of the first line provided on an upper layer of the predetermined layer have same upper end positions and lower end positions in the laminating direction,
 the first contact plug is extended through the layer, in which the contact connecting portion of the first line connected to the second contact plug is formed, to an upper layer with no contact to the contact connecting portion. 
 
     
     
       17. The nonvolatile semiconductor memory device according to  claim 10 , wherein a through-hole is made in the contact connecting portion, and
 the contact plug is formed in the through-hole. 
 
     
     
       18. The nonvolatile semiconductor memory device according to claim 1, further comprising a transistor formed above the semiconductor substrate and under the cell array.  
     
     
       19. The nonvolatile semiconductor memory device according to claim 10, further comprising a transistor formed above the semiconductor substrate and under the cell array.  
     
     
       20. A nonvolatile semiconductor memory device comprising:
 a semiconductor substrate; and   a cell array formed above the semiconductor substrate, including first lines, second lines intersecting the first lines, and memory cells connected at intersections of the first and second lines between both lines, wherein   the cell array includes:   a memory cell region where the memory cells are formed; and   a peripheral region that is provided around the memory cell region,   in the memory cell region, the first lines are extended in parallel with a first direction, the first lines are repeatedly formed at first intervals in a second direction orthogonal to the first direction, the first lines have a first width thinner than 40 nm in the second direction, and the second lines are extended in parallel with the second direction,   in the peripheral region, contact connecting portions are disposed on one end side and the other end side in the first direction of the first line,   the contact connecting portion is formed so as to contact with a contact plug extended in a laminating direction orthogonal to both of the first direction and the second direction,   the contact connecting portions have a second width in the second direction which is larger than the first width, and   the contact connecting portions have a first portion extended in the first direction which has a first width in the second direction.    
     
     
       21. The nonvolatile semiconductor memory device according to claim 20, wherein
 in the peripheral region, the first lines located at (4m−3)-th (m is a positive odd number), (4m−2)-th, (4m+1)-th and (4m+2)-th positions in the second direction from a predetermined position have the contact connecting portions on one end side in the first direction of the first line,   in the peripheral region, the first lines located at (4m−1)-th, 4m-th, (4m+3)-th and (4m+4)-th positions in the second direction from the predetermined position have the contact connecting portions on the other end side in the first direction of the first line, and   the contact connecting portions at the (4m−1)-th and the 4m-th positions are formed in a range from the first line located at the (4m+2)-th position to the first line located at the (4m−3)-th position in the second direction.    
     
     
       22. The nonvolatile semiconductor memory device according to claim 20, wherein
 the contact connecting portions include:   a first connecting portion connected to one of the first lines, and   a second connecting portion connected to other of the first lines adjacent to the one of the first lines, and wherein   the first portion of the first connecting portion and the first portion of the second connecting portion are disposed on straight line in the first direction.    
     
     
       23. The nonvolatile semiconductor memory device according to claim 20, the device further includes:
 a transistor formed above the semiconductor substrate and under the cell array.