Analog to digital conversion for a CMOS imager

Abstract

An image sensor system using offset analog to digital converters. The analog to digital converters require a plurality of clock cycles to carry out the actual conversion. These conversions are offset in time from one another, so that at each clock cycle, new data is available.A CMOS image sensor converts successive analog signals, representing at least a portion of an image, into successive digital signals using an analog to digital circuit block. Multiple clock cycles may be used by the circuit block to fully convert an analog signal into a corresponding digital signal. The conversion of one analog signal into a corresponding digital signal by the circuit block may be offset in time and partially overlapping with the conversion of a successive analog signal into its corresponding successive digital signal by the circuit block.

What is claimed is: 
     
       1. An analog-to-digital (A/D) converter, comprising:
 an input, for receiving a series of analog signals;   an output, for outputting a series of digital signals respectively corresponding to said series of analog signals;   a plurality of A/D cells, each of said A/D cells for converting one of said series of analog signals to a corresponding one of said series of digital signals; and   a control circuit, coupled to said input, said output, and said plurality of A/D cells;   wherein said control circuit operates said input, said output, and said plurality of A/D cells so that each successive A/D cell is assigned, at a different time, to convert a different one of each successive analog signal from said series of analog signals to a corresponding digital signal in said series of digital signals.   
     
     
       2. The analog-to-digital converter of  claim 1 , wherein said different time correspond to a different period of a clock signal provided to said analog-to-digital converter. 
     
     
       3. The analog-to-digital converter of  claim 1 , wherein each of said A/D cells further comprises a calibration element, said calibration element being set so that each A/D cell coverts the same analog signal present at said input to a same digital value at said output. 
     
     
       4. The analog-to-digital converter of  claim 1 , wherein each of said A/D cells further comprises a noise suppression element. 
     
     
       5. The analog-to-digital converter of  claim 4 , wherein said noise suppression element comprises a transistor. 
     
     
       6. The analog-to-digital converter of  claim 1 , wherein each A/D cell performs an A/D conversion in a same amount of time. 
     
     
       7. The analog-to-digital converter of  claim 1 , wherein each A/D cell performs an A/D conversion using successive approximation. 
     
     
       8. The analog-to-digital converter of  claim 1 , wherein said control circuit operates to cause said analog-to-digital converter to begin converting a different one of said series of analog signals on each of a series of successive clock signals. 
     
     
       9. The analog-to-digital converter of  claim 1 , wherein said control circuit operates to cause said analog-to-digital converter to output a series of digital signals on each of a series of successive clock signals. 
     
     
       10. A method for converting a series of analog signals to a corresponding series of digital signals, comprising:
 receiving over a period of time, a series of analog signals;   assigning each analog signal from said series of analog signals as they are received to an available A/D cell for analog-to-digital conversion to a corresponding digital signal; and   outputting a different digital signal corresponding to a respective analog signal from said series of analog signals as each A/D cell finishes its analog-to-digital conversion;   wherein at least two A/D cells are performing respective analog-to-digital conversions while another A/D cell outputs one of said digital signals.   
     
     
       11. The method of  claim 10 , further comprising:
 calibrating each A/D cell so that an analog-to-digital conversion performed on a same analog signal by any A/D cell results in a same digital signal.   
     
     
       12. The method of  claim 10 , wherein said step of assigning comprises a step of suppressing comparator kickback noise during said analog-to-digital conversion. 
     
     
       13. The method of  claim 10 , wherein each A/D cell performs an analog-to-digital conversion in a same amount of time. 
     
     
       14. The method of  claim 10 , wherein each A/D cell perform an analog-to-digital conversion using successive approximation. 
     
     
       15. A method comprising:
 receiving light on an array of photoreceptors of a CMOS imager, the light forming at least a portion of an image;   converting the light into successive analog signals;   providing the successive analog signals to an input of an analog to digital (A/D) converter of the CMOS imager during a first period of time; and   determining at least one bit of respective successive digital signals corresponding to the successive analog signals, respectively, during a second period of time that begins after the first period of time ends.   
     
     
       16. The method of claim 15, wherein determining the at least one bit comprises determining a final bit of the respective successive digital signals. 
     
     
       17. The method of claim 16, wherein the determining the final bit comprises determining the tenth bit of the respective successive digital signals. 
     
     
       18. The method of claim 15, wherein providing the successive analog signals comprises providing at least four successive analog signals. 
     
     
       19. The method of claim 18, wherein determining the at least one bit comprises determining at least four bits. 
     
     
       20. The method of claim 15, wherein determining the at least one bit comprises determining at least four bits. 
     
     
       21. A method comprising:
 converting an image impinging upon a CMOS imager array into analog signals;   providing a first analog signal associated with the image to an input of an analog to digital (A/D) converter of the CMOS imager, and, during a first time period, the A/D converter converting the first analog signal into a corresponding first digital signal;   providing a second analog signal associated with the image to the input of the A/D converter, and, during a second time period, the A/D converter converting the second analog signal into a corresponding second digital signal; and   providing a third analog signal associated with the image to the input of the A/D converter, and, during a third time period, the A/D converter converting the third analog signal into a corresponding third digital signal, wherein the first, second, and third time periods are offset from each other and partially overlapping.   
     
     
       22. The method of claim 21, further comprising providing a fourth analog signal associated with the image to the input of the A/D converter, and, during a fourth time period, the A/D converter converting the fourth analog signal into a corresponding fourth digital signal, wherein the first, second, third, and fourth time periods are offset from each other and partially overlapping. 
     
     
       23. The method of claim 22, wherein by the time the fourth period of time begins, the A/D converter has determined at least some, but not all, of the bits of the first digital signal. 
     
     
       24. The method of claim 21, wherein the first, second, and third time periods are offset from each other by one clock cycle. 
     
     
       25. The method of claim 21, wherein the first, second, and third analog signals are successive. 
     
     
       26. The method of claim 25, wherein by the time the third period of time begins, the A/D converter has determined at least one of the bits of the first digital signal. 
     
     
       27. The method of claim 21, wherein when the third period of time begins, the A/D converter has determined some, but not all, of the bits of the first digital signal. 
     
     
       28. The method of claim 21, wherein during the partially overlapping time period of the first, second, and third time periods, different bits of the first, second, and third digital signals are determined during identical clock cycles.