DLL circuit adapted to semiconductor device

Abstract

A DLL circuit is designed to adjust the delay time and the duty applied to an input clock signal, thus producing a DLL clock signal. In a non-clocking state of the DLL clock signal in which pulses disappear temporarily, the DLL circuit stops updating the delay time and the duty of the DLL clock signal. That is, the DLL circuit is capable of preventing a phase difference between the input clock signal and the DLL clock signal from being erroneously detected in the non-clocking state of the DLL clock signal, thus preventing the delay time and the duty from being updated based on the erroneously detected phase difference. Thus, it is possible to reduce the number of cycles adapted to the delay-locked control and to thereby stabilize the operation of the DLL circuit.

What is claimed is: 
     
       1. A DLL circuit adjusting a duty of an input clock signal, comprising:
 a duty control circuit that produces a duty signal to control the duty of the input clock signal; 
 a duty adjustment circuit that adjusts the duty of the input clock signal based on the duty signal, thus producing a DLL clock signal; and 
 a DLL clock detection circuit that detects either a clocking state or a non-clocking state with respect to the DLL clock signal, 
 wherein the DLL clock detection circuit controls the duty control circuit to produce the duty signal to change the DLL clock signal from the non-clocking state to the clocking state when the DLL clock detection circuit detects the non-clocking state with respect to the DLL clock signal. 
 
     
     
       2. A DLL circuit comprising:
 a duty control circuit that produces a duty signal to control a duty of a first clock signal input thereto; 
 a duty adjustment circuit that adjusts the duty of the first clock signal based on the duty signal, thus producing a second clock signal; 
 a delay control circuit that produces a delay signal to control a delay time applied to the second clock signal; 
 a delay circuit that applies the delay time to the second clock signal based on the delay signal, thus producing a DLL clock signal; and 
 a DLL clock detection circuit that detects either a clocking state or a non-clocking state with respect to the DLL clock signal, 
 wherein the DLL clock detection circuit controls at least one of the duty control circuit and the delay control to produce corresponding one or ones of the duty signal and the delay signal to change the DLL clock signal from the non-clocking state to the clocking state when the DLL clock detection circuit detects the non-clocking state of the DLL clock signal. 
 
     
     
       3. A DLL circuit adjusting a phase of an input clock signal, comprising:
 a delay control circuit that produces a delay signal to control a delay time applied to the input clock signal; 
 a delay circuit that applies the delay time to the input clock signal based on the delay signal, thus producing a DLL clock signal; and 
 a DLL clock detection circuit that detects either a clocking state or a non-clocking state with respect to the DLL clock signal, 
 wherein the DLL clock detection circuit controls the delay control circuit to produce the delay signal to change the DLL clock signal from the non-clocking state to the clocking state when the DLL clock detection circuit detects the non-clocking state with respect to the DLL clock signal, and 
 wherein the DLL clock signal and a DLL clock detection enable signal for periodically activating the DLL clock detection circuit are supplied to the DLL clock detection circuit, which includes a counter for counting a number of pulses included in the DLL clock signal during activation of the DLL clock detection enable signal, and a latch circuit for declaring the clocking state of the DLL clock signal when the counted number is greater than a prescribed number and for declaring the non-clocking state of the DLL clock signal when the counted number is less than the prescribed number. 
 
     
     
       4. The DLL circuit according to  claim 1 , wherein the DLL clock signal and a DLL clock detection enable signal for periodically activating the DLL clock detection circuit are supplied to the DLL clock detection circuit, which includes a counter for counting a number of pulses included in the DLL clock signal during activation of the DLL clock detection enable signal, and a latch circuit for declaring the clocking state of the DLL clock signal when the counted number is greater than a prescribed number and for declaring the non-clocking state of the DLL clock signal when the counted number is less than the prescribed number. 
     
     
       5. A DLL circuit adjusting a phase of an input clock signal, comprising:
 a delay control circuit that produces a delay signal to control a delay time applied to the input clock signal; 
 a delay circuit that applies the delay time to the input clock signal based on the delay signal, thus producing a DLL clock signal; 
 a DLL clock detection circuit that detects either a clocking state or a non-clocking state with respect to the DLL clock signal; 
 a DQ buffer for buffering the DLL clock signal; 
 a DQ replica circuit for receiving the DLL clock signal so as to output a DQ replica output signal; and 
 a phase detection circuit for detecting a phase difference between the input clock signal and the DQ replica output signal, thus producing a phase detection result, 
 wherein the DLL clock detection circuit controls the delay control circuit to produce the delay signal to change the DLL clock signal from the non-clocking state to the clocking state when the DLL clock detection circuit detects the non-clocking state with respect to the DLL clock signal, 
 wherein the delay control circuit includes a latch circuit for latching the delay time presently applied to the DLL clock signal, and an adder for adding the phase difference to the delay time based on the phase detection result so as to produce an addition result, and 
 wherein the addition result of the adder is latched by the latch circuit as a new delay time when the DLL clock detection circuit declares the clocking state of the DLL clock signal. 
 
     
     
       6. The DLL circuit according to  claim 1  further comprising a duty detection circuit including a duty detector for detecting the duty of the DLL clock signal, a latch circuit for latching a stacked level of the DLL clock signal, and a selector for selecting an output signal of the duty detector when the DLL clock detection circuit declares the non-clocking state of the DLL clock signal and for selecting the stacked level or its inverted level when the DLL clock detection circuit declares the non-clocking state of the DLL clock signal. 
     
     
       7. A semiconductor device including the DLL circuit according to  claim 1 . 
     
     
       8. A semiconductor device comprising:
 a control circuit that responds to first and second feedback signals to produce a control signal; and 
 a DLL clock signal generation circuit that receives an input clock signal and the control signal and generates a DLL clock signal that is related to the input clock signal and controlled in at least one of a phase and a duty in response to the control signal, 
 wherein the first feedback signal is produced in response to at least the DLL clock signal and the second feedback signal that is produced in response to the DLL clock signal unchanged in a logic level during at least one cycle of the input clock signal. 
 
     
     
       9. The semiconductor device according to  claim 8 , wherein the DLL clock signal generation circuit comprises a duty adjustment circuit, and wherein the control circuit comprises a duty control circuit that is coupled to receive the first and second feedback signals and supplies the control signal to the duty adjustment circuit to adjust a duty of the DLL clock signal. 
     
     
       10. The semiconductor device according to  claim 9 , wherein the DLL clock signal generation circuit further comprises a delay circuit coupled in series with the duty adjustment circuit, wherein the control circuit further comprises a delay control circuit that produces an additional control signal in response to the first and second feedback signals, and wherein the additional control signal is supplied to the delay circuit to delay the DLL clock signal with respect to the input clock signal. 
     
     
       11. The semiconductor device according to  claim 10 , wherein the first feedback signal is produced in response to the input clock signal. 
     
     
       12. the semiconductor device according to  claim 8 , wherein the DLL clock signal generation circuit comprises a delay circuit, wherein the control circuit comprises a delay control circuit, wherein the first feedback signal is produced in response to the input clock signal and the DLL clock signal, and wherein the delay control circuit is coupled to receive the first and second feedback signals and supplies the control signal to the delay circuit to delay the DLL clock signal with respect to the input clock signal. 
     
     
       13. The semiconductor device according to  claim 12 , wherein the DLL clock signal generation circuit further comprises a duty adjustment circuit coupled in series with the delay circuit, wherein the control circuit further comprises a duty control circuit that produces an additional control signal in response to the DLL clock signal and the second feedback signal, and wherein the additional control signal is supplied to the duty adjustment circuit to control a duty of the DLL clock signal. 
     
     
       14. A delay locked loop (DLL) circuit comprising:
 a delay control circuit that produces a delay signal to control a delay time applied to an input clock signal;   a delay circuit that applies the delay time to the input clock signal based on the delay signal, thus producing a DLL clock signal; and   a clock detection circuit that detects either a clocking state or a non-clocking state with respect to a clock signal based on the input clock signal,   wherein the clock detection circuit controls the delay control circuit to prevent updates to the delay signal when the non-clocking state is detected and to allow updates to the delay signal when the clocking state is detected.   
     
     
       15. The DLL circuit of claim 14, wherein the clock signal based on the input clock signal is the DLL clock signal. 
     
     
       16. The DLL circuit of claim 14, wherein the clock detection circuit comprises a plurality of D-type latches, a first latch among the plurality of D-type latches having an output terminal connected to an input terminal of a second latch among the plurality of D-type latches. 
     
     
       17. The DLL circuit of claim 16, wherein the clock detection circuit allows updates to the delay signal when the plurality of D-type latches each have the same logic level on respective output terminals. 
     
     
       18. The DLL circuit of claim 14, further comprising a duty control circuit and a duty adjustment circuit to adjust the duty of the DLL clock signal. 
     
     
       19. The DLL circuit of claim 18, wherein the duty control circuit controls the duty adjustment circuit to adjust the duty of the DLL clock signal to approximately 50%. 
     
     
       20. The DLL circuit of claim 18, wherein the clock detection circuit controls the duty control circuit to prevent adjustment of the duty of the DLL clock signal when the non-clocking state is detected and to allow adjustment of the duty of the DLL clock signal when the clocking state is detected.