Driving circuit of a liquid crystal display panel

Abstract

A driving circuit of a liquid crystal display panel includes a substrate, a plurality of driver IC chips located on the substrate, a current supplier, and a first conductive wire set. The first conductive wire set has a plurality of conductive wire segments for connecting the driver IC chips in parallel to the current supplier. Furthermore, the conductive wire segments each have a form, such that paths formed of the conductive wire segments from the current supplier to the respective driver IC chips have an equal resistance, and, accordingly, each of the driver IC chips obtain the same input voltage. Hence, a problem of band mura is avoided.

What is claimed is: 
     
       1. A driving circuit of a liquid crystal display panel, comprising:
 a substrate; 
 a plurality of driver IC chips positioned on the substrate; 
 a current supplier; and 
 a first conductive wire set comprising a conductive wire for paths electrically connecting each of the plurality of driver IC chips in parallel to the current supplier, wherein each conductive wire path electrically connecting one of the plurality of IC chips in parallel to the current supplier has approximately equal resistance, wherein a first of the conductive wire paths electrically connecting a first IC chip to the current supplier comprises a first wire segment and a second wire segment, and wherein a second of the conductive wire paths electrically connecting a second IC chip to the current supplier comprises the first wire segment and a third wire segment. 
 
     
     
       2. The driving circuit of  claim 1 , wherein the conductive wire and the driver IC chips are electrically connected by paths comprise a plurality of conductive wire segments, and each conductive wire segment of the plurality of conductive wire segments each have has a form, such that paths formed of the conductive wire segments from the current supplier to the respective driver IC chips each have an equal resistance and each of the plurality of driver IC chips obtain obtains a same input voltage from the current supplier. 
     
     
       3. The driving circuit of  claim 1 , wherein the first conductive wire set comprises a metal layer, alloy layer, or indium tin oxide (ITO) layer. 
     
     
       4. The driving circuit of  claim 1 , wherein the substrate further comprises a plurality of scanning lines and a plurality of signal lines. 
     
     
       5. The driving circuit of  claim 4 , wherein the plurality of driver IC chips are configured to output switch/addressing signals to the plurality of scanning lines. 
     
     
       6. The driving circuit of  claim 4 , wherein the plurality of driver IC chips are configured to output image information signals to the plurality of signal lines. 
     
     
       7. The driving circuit of  claim 4 , wherein the first conductive wire set comprises a same material as the plurality of scanning lines. 
     
     
       8. The driving circuit of  claim 4 , wherein the first conductive wire set comprises a same material as the plurality of signal lines. 
     
     
       9. The A driving circuit of  claim 1  a liquid crystal display panel, further comprises 1  comprising:
 a substrate; 
 a plurality of driver IC chips positioned on the substrate; 
 a current supplier; 
 a first conductive wire set arranged to electrically connect a first of the plurality of driver IC chips to the current supplier, the first conductive wire set comprising a first wire segment and a second wire segment; and 
 a second conductive wire set comprising a conductive wire for arranged to electrically connecting connect a second of the plurality of driver IC chips in parallel to the current supplier, the second conductive wire set comprising the first wire segment and a third wire segment, 
 wherein the second wire segment has a length and a cross section that are different than a length and a cross section of the third wire segment such that the first conductive wire set and the second conductive wire set have approximately equal resistance. 
 
     
     
       10. The driving circuit of  claim 9 , wherein the conductive wire included in the second conductive wire set and each of the driver IC chips are electrically connected by a conductive wire segment, and the first, second, and third conductive wire segments each have a form, such that paths formed of the second conductive wire segments from the current supplier to the respective driver IC chips have an equal resistance and each of the plurality of driver IC chips obtain obtains a same input voltage. 
     
     
       11. The driving circuit of  claim 9 , wherein the first and second conductive wire set carries sets carry at least one of a thin film transistor on-state current and the second conductive wire set carries a thin film transistor off-state current. 
     
     
       12. The driving circuit of  claim 9 , wherein the second conductive wire set comprises a metal layer, alloy layer, or indium tin oxide (ITO) layer. 
     
     
       13. The driving circuit of  claim 9 , wherein the substrate further comprises a plurality of scanning lines and a plurality of signal lines. 
     
     
       14. The driving circuit of  claim 13 , wherein the plurality of driver IC chips are configured to output switch/addressing signals to the plurality of scanning lines. 
     
     
       15. The driving circuit of  claim 13 , wherein the plurality of driver IC chips are configured to output image information signals to the plurality of signal lines. 
     
     
       16. The driving circuit of  claim 13 , wherein the second conductive wire set comprises a same material as the plurality of scanning lines. 
     
     
       17. The driving circuit of  claim 13 , wherein the second conductive wire set comprises a same material as the plurality of signal lines. 
     
     
       18. A driving circuit of a liquid crystal display panel, comprising:
 a substrate;   a current supplier;   a first driver IC chip positioned on the substrate; and   a second driver IC chip positioned on the substrate,   wherein the first and second driver IC chips are electrically connected to the current supplier in parallel via a first wire set electrically connecting the first driver IC chip and the second driver IC chip to the current supplier in parallel, and a second wire set electrically connecting the first driver IC chip and the second driver IC chip to the current supplier in parallel,   wherein the first wire set is physically distinct from the second wire set, and   wherein the first wire set is configured to carry a first current to each of the first and second driver IC chips, wherein the second wire set is configured to carry a second current to each of the first and second driver IC chips, and wherein the first current is different from the second current.   
     
     
       19. The driving circuit of claim 18, wherein at least one of the first and second wire sets comprises a first electrical connection from the current supplier to the first driver IC chip and a second electrical connection from the current supplier to the second driver IC chip, and wherein the first electrical connection is configured to provide the first driver IC chip with a first input voltage and the second electrical connection is configured to provide the second driver IC chip with a second input voltage that is substantially the same as the first input voltage. 
     
     
       20. The driving circuit of claim 18, wherein at least one of the first and second wire sets comprises a first electrical connection from the current supplier to the first driver IC chip and a second electrical connection from the current supplier to the second driver IC chip, and wherein the first electrical connection has a first electrical resistance and wherein the second electrical connection has a second electrical resistance that is substantially the same as the first electrical resistance. 
     
     
       21. The driving circuit of claim 18, wherein:
 at least one of the first and second wire sets comprises a first electrical connection from the current supplier to the first driver IC chip and a second electrical connection from the current supplier to the second driver IC chip;   the first electrical connection comprises a main wire segment and a first branch wire segment; and   the second electrical connection comprises the main wire segment and a second branch wire segment.   
     
     
       22. The driving circuit of claim 18, wherein the substrate comprises a plurality of scanning lines and a plurality of signal lines. 
     
     
       23. The driving circuit of claim 22, wherein the first driver IC chip and the second driver IC chip are each configured to output signals to one or more of the plurality of scanning lines. 
     
     
       24. The driving circuit of claim 18, wherein:
 the first wire set comprises a first electrical connection from the current supplier to the first driver IC chip and a second electrical connection from the current supplier to the second driver IC chip;   the second wire set comprises a third electrical connection from the current supplier to the first driver IC chip and a fourth electrical connection from the current supplier to the second driver IC chip;   the first electrical connection is configured to provide the first driver IC chip with a first input voltage;   the second electrical connection is configured to provide the second driver IC chip with an input voltage that is substantially the same as the first input voltage;   the third electrical connection is configured to provide the first driver IC chip with a second input voltage; and   the fourth electrical connection is configured to provide the second driver IC chip with an input voltage that is substantially the same as the second input voltage.   
     
     
       25. The driving circuit of claim 18, wherein:
 the first wire set comprises a first electrical connection from the current supplier to the first driver IC chip and a second electrical connection from the current supplier to the second driver IC chip;   the second wire set comprises a third electrical connection from the current supplier to the first driver IC chip and a fourth electrical connection from the current supplier to the second driver IC chip;   the first electrical connection has a first electrical resistance;   the second electrical connection has an electrical resistance that is substantially the same as the first electrical resistance;   the third electrical connection has a second electrical resistance; and   the fourth electrical connection has an electrical resistance that is substantially the same as the second electrical resistance.   
     
     
       26. The driving circuit of claim 18, wherein:
 the first wire set comprises a first electrical connection from the current supplier to the first driver IC chip and a second electrical connection from the current supplier to the second driver IC chip;   the second wire set comprises a third electrical connection from the current supplier to the first driver IC chip and a fourth electrical connection from the current supplier to the second driver IC chip;   the first electrical connection comprises a first main wire segment and a first branch wire segment;   the second electrical connection comprises the first main wire segment and a second branch wire segment;   the third electrical connection comprises a second main wire segment and a third branch wire segment; and   the fourth electrical connection comprises the second main wire segment and a fourth branch wire segment.   
     
     
       27. The driving circuit of claim 18, wherein the first current is an on-state current and the second current is an off-state current.