Non-volatile semiconductor storage device

Abstract

Memory strings includes: a first semiconductor layer including a columnar portion extending in a direction perpendicular to a substrate; a first electric charge storage layer formed to surround a side surface of the columnar portion; and a first conductive layer formed to surround the first electric charge storage layer. First selection transistors includes: a second semiconductor layer extending upward from a top surface of the columnar portion; a second electric charge storage layer formed to surround a side surface of the second semiconductor layer; and a second conductive layer formed to surround the second electric charge storage layer. The non-volatile semiconductor storage device further includes a control circuit that causes, prior to reading data from a selected one of the memory strings, electric charges to be accumulated in the second electric charge storage layer of one of the first selection transistors connected to an unselected one of the memory strings.

What is claimed is: 
     
       1. A non-volatile semiconductor storage device comprising:
 a plurality of memory strings, each having a plurality of electrically rewritable memory cells connected in series; and 
 a plurality of first selection transistors connected to one ends of the respective memory strings, 
 each of the memory strings comprising:
 a first semiconductor layer including a columnar portion extending in a direction perpendicular to a substrate; 
 a first electric charge storage layer formed to surround a side surface of the columnar portion; and 
 a first conductive layer formed to surround a side surface of the columnar portion as well as the first electric charge storage layer, the first conductive layer functioning as a control electrode of a respective one of the memory cells, 
 
 each of the first selection transistors comprising:
 a second semiconductor layer extending upward from a top surface of the columnar portion; 
 a second electric charge storage layer formed to surround a side surface of the second semiconductor layer; and 
 a second conductive layer formed to surround a side surface of the second semiconductor layer as well as the second electric charge storage layer, the second conductive layer functioning as a control electrode of a respective one of the first selection transistors, 
 
 the non-volatile semiconductor storage device further comprising a control circuit configured to cause, prior to reading data from a selected one of the memory strings, electric charges to be accumulated in the second electric charge storage layer of one of the first selection transistors connected to an unselected one of the memory strings. 
 
     
     
       2. The non-volatile semiconductor storage device according to  claim 1 , wherein
 a plurality of memory blocks each includes a plurality of the memory strings arranged in a matrix form, and 
 prior to reading data from a selected one of the memory strings in a selected one of the memory blocks, the control circuit causes electric charges to be accumulated in the second electric charge storage layer of one of the first selection transistors connected to an unselected one of the memory strings in the selected memory block. 
 
     
     
       3. The non-volatile semiconductor storage device according to  claim 1 , wherein
 a plurality of memory blocks each includes a plurality of the memory strings arranged in a matrix form, and 
 prior to reading data from a selected one of the memory strings in a selected one of the memory blocks, the control circuit causes electric charges to be accumulated in the second electric charge storage layers of the first selection transistors connected to the memory strings in an unselected one of the memory blocks. 
 
     
     
       4. The non-volatile semiconductor storage device according to  claim 1 , wherein
 a plurality of memory blocks each includes a plurality of the memory strings arranged in a matrix form, and 
 prior to reading data from a selected one of the memory strings in a selected one of the memory blocks, the control circuit causes electric charges to be accumulated in the second electric charge storage layer of one of the first selection transistors connected to an unselected one of the memory strings in the selected memory block, and also causes electric charges to be accumulated in the second electric charge storage layers of the first selection transistors connected to the memory strings in an unselected one of the memory blocks. 
 
     
     
       5. The non-volatile semiconductor storage device according to  claim 1 , wherein
 after reading data from a selected one of the memory strings, the control circuit causes electric charges to be discharged from the second electric charge storage layer of one of the first selection transistors connected to an unselected one of the memory strings. 
 
     
     
       6. The non-volatile semiconductor storage device according to  claim 5 , wherein
 the control circuit is configured to generate a GIDL current near a gate of one of the first selection transistors connected to an unselected one of the memory strings to boost a voltage at the second semiconductor layer to a first voltage by the GIDL current, 
 thereby discharging electric charges stored in the second electric charge storage layer. 
 
     
     
       7. The non-volatile semiconductor storage device according to  claim 1 , wherein
 the control circuit causes electric charges to be accumulated in the second electric charge storage layer by boosting in a step-like manner to be applied to a gate of one of the first selection transistors connected to an unselected one of the memory strings. 
 
     
     
       8. The non-volatile semiconductor storage device according to  claim 1 , comprising:
 a plurality of second selection transistors connected to the other ends of the memory strings, 
 wherein each of the second selection transistors comprises:
 a third semiconductor layer extending downward from a bottom surface of the first semiconductor layer; 
 a third electric charge storage layer formed to surround a side surface of the third semiconductor layer; and 
 a third conductive layer formed to surround a side surface of the third semiconductor layer as well as the third electric charge storage layer, the third conductive layer functioning as a control electrode of a respective one of the second selection transistors, and 
 
 prior to reading data from a selected one of the memory strings, the control circuit causes electric charges to be accumulated in the third electric charge storage layer of one of the second selection transistors connected to an unselected one of the memory strings. 
 
     
     
       9. The non-volatile semiconductor storage device according to  claim 8 , wherein
 a plurality of memory blocks each includes a plurality of the memory strings arranged in a matrix form, and 
 prior to reading data from a selected one of the memory strings in a selected one of the memory blocks, the control circuit causes electric charges to be accumulated in the third electric charge storage layer of one of the second selection transistors connected to an unselected one of the memory strings in the selected memory block. 
 
     
     
       10. The non-volatile semiconductor storage device according to  claim 8 , wherein
 a plurality of memory blocks each includes a plurality of the memory strings arranged in a matrix form, and 
 prior to reading data from a selected one of the memory strings in a selected one of the memory blocks, the control circuit causes electric charges to be accumulated in the third electric charge storage layers of the second selection transistors connected to the memory strings in an unselected one of the memory blocks. 
 
     
     
       11. The non-volatile semiconductor storage device according to  claim 8 , wherein
 a plurality of memory blocks each includes a plurality of the memory strings arranged in a matrix form, and 
 prior to reading data from a selected one of the memory strings in a selected one of the memory blocks, the control circuit causes electric charges to be accumulated in the third electric charge storage layer of one of the second selection transistors connected to an unselected one of the memory strings in the selected memory block, and also causes electric charges to be accumulated in the third electric charge storage layers of the second selection transistors connected to the memory strings in an unselected one of the memory blocks. 
 
     
     
       12. The non-volatile semiconductor storage device according to  claim 8 , wherein
 after reading data from a selected one of the memory strings, the control circuit causes electric charges to be discharged from the third electric charge storage layer of one of the second selection transistors connected to an unselected one of the memory strings. 
 
     
     
       13. The non-volatile semiconductor storage device according to  claim 12 , wherein
 the control circuit is configured to generate a GIDL current near a gate of one of the second selection transistors connected to an unselected one of the memory strings to boost a voltage at the third semiconductor layer to a second voltage by the GIDL current, 
 thereby discharging electric charges stored in the third electric charge storage layer. 
 
     
     
       14. The non-volatile semiconductor storage device according to  claim 8 , wherein
 the control circuit causes electric charges to be accumulated in the third electric charge storage layer by boosting in a step-like manner a voltage to be applied to a gate of one of the second selection transistors connected to an unselected one of the memory strings. 
 
     
     
       15. The non-volatile semiconductor storage device according to  claim 1 , wherein
 the first semiconductor layer comprises a joining portion formed to join bottom ends of a pair of the columnar portions. 
 
     
     
       16. A non-volatile semiconductor storage device comprising:
 a plurality of memory strings, each having a plurality of electrically rewritable memory cells connected in series; and 
 a plurality of first selection transistors connected to one ends of the respective memory strings, 
 each of the memory strings comprising:
 a first semiconductor layer including a columnar portion extending in a direction perpendicular to a substrate; 
 a first electric charge storage layer formed to surround a side surface of the columnar portion; and 
 a first conductive layer formed to surround a side surface of the columnar portion as well as the first electric charge storage layer, the first conductive layer functioning as a control electrode of a respective one of the memory cells, 
 
 each of the first selection transistors comprising:
 a second semiconductor layer extending downward from a bottom surface of the columnar portion; 
 a second electric charge storage layer formed to surround a side surface of the second semiconductor layer; and 
 a second conductive layer formed to surround a side surface of the second semiconductor layer as well as the second electric charge storage layer, the second conductive layer functioning as a control electrode of a respective one of the first selection transistors, 
 
 the non-volatile semiconductor storage device further comprising a control circuit configured to cause, prior to reading data from a selected one of the memory strings, electric charges to be accumulated in the second electric charge storage layer of one of the first selection transistors connected to an unselected one of the memory strings. 
 
     
     
       17. The non-volatile semiconductor storage device according to  claim 16 , wherein
 a plurality of memory blocks each includes a plurality of the memory strings arranged in a matrix form, and 
 prior to reading data from a selected one of the memory strings in a selected one of the memory blocks, the control circuit causes electric charges to be accumulated in the second electric charge storage layer of one of the first selection transistors connected to an unselected one of the memory strings in the selected memory block. 
 
     
     
       18. The non-volatile semiconductor storage device according to  claim 16 , wherein
 a plurality of memory blocks each includes a plurality of the memory strings arranged in a matrix form, and 
 prior to reading data from a selected one of the memory strings in a selected one of the memory blocks, the control circuit causes electric charges to be accumulated in the second electric charge storage layers of the first selection transistors connected to the memory strings in an unselected one of the memory blocks. 
 
     
     
       19. The non-volatile semiconductor storage device according to  claim 16 , wherein
 a plurality of memory blocks each includes a plurality of the memory strings arranged in a matrix form, and 
 prior to reading data from a selected one of the memory strings in a selected one of the memory blocks, the control circuit causes electric charges to be accumulated in the second electric charge storage layer of one of the first selection transistors connected to an unselected one of the memory strings in the selected memory block, and also causes electric charges to be accumulated in the second electric charge storage layers of the first selection transistors connected to the memory strings in an unselected one of the memory blocks. 
 
     
     
       20. The non-volatile semiconductor storage device according to  claim 16 , wherein
 after reading data from a selected one of the memory strings, the control circuit causes electric charges to be discharged from the second electric charge storage layer of one of the first selection transistors connected to an unselected one of the memory strings. 
 
     
     
       21. A non-volatile semiconductor storage device comprising:
 a first memory string including memory cells electrically coupled in series;   a first selection transistor electrically coupled to one end of the first memory string;   a word line electrically coupled to a gate of one of the memory cells;   a first line electrically coupled to the first selection transistor; and   a controller configured to perform an erase operation on the condition that an erase voltage is applied to the first line, a first voltage is applied to a gate of the first selection transistor, and the erase voltage is higher than the first voltage,   the controller being configured to perform a program operation on the condition that a program voltage is applied to the gate of the first selection transistor, a second voltage is applied to the first line, a third voltage is applied to the word line, the program voltage is higher than the second voltage, and the program voltage is higher than the third voltage.   
     
     
       22. The non-volatile semiconductor storage device according to claim 21, wherein the second voltage is zero voltage. 
     
     
       23. The non-volatile semiconductor storage device according to claim 21, further comprising:
 a second selection transistor electrically coupled to the other end of the first memory string;   a second line electrically coupled to the second selection transistor; and   wherein the second voltage is applied to a gate of the second selection transistor in the program operation.   
     
     
       24. The non-volatile semiconductor storage device according to claim 22, further comprising:
 a second selection transistor electrically coupled to the other end of the first memory string;   a second line electrically coupled to the second selection transistor; and   wherein zero is applied to a gate of the second selection transistor in the program operation.   
     
     
       25. The non-volatile semiconductor storage device according to claim 21, further comprising:
 word lines electrically coupled to the memory cells; and   wherein the second voltage is applied to the word lines in the program operation.   
     
     
       26. The non-volatile semiconductor storage device according to claim 23, further comprising:
 a second memory string including memory cells electrically coupled in series; and wherein either the first line or the second line electrically coupled to both the first memory string and the second memory string.   
     
     
       27. A method of controlling a non-volatile semiconductor storage device including a first memory string, in which memory cells are coupled in series, a first selection transistor electrically coupled to one end of the first memory string, a word line electrically coupled to a gate of one of the memory cells, and a first line electrically coupled to the first selection transistor, comprising:
 erasing on the condition that an erase voltage is applied to the first line, a first voltage is applied to a gate of the first selection transistor, and the erase voltage is higher than the first voltage; and   programming on the condition that a program voltage is applied to the gate of the first selection transistor, a second voltage is applied to the first line, a third voltage is applied to the word line, the program voltage is higher than the second voltage, and the program voltage is higher than the third voltage.   
     
     
       28. The method according to claim 27, wherein the erasing is an erasing for a cell of the first memory string and the programming is a programming for the first selection transistor. 
     
     
       29. The method according to claim 27, wherein the second voltage is zero voltage. 
     
     
       30. The method according to claim 27, wherein the non-volatile semiconductor storage device further comprising:
 a second selection transistor electrically coupled to the other end of the first memory string;   a second line electrically coupled to the second selection transistor; and   wherein the second voltage is applied to a gate of the second selection transistor in the programming.   
     
     
       31. The method according to claim 29, wherein the non-volatile semiconductor storage device further comprising:
 a second selection transistor electrically coupled to the other end of the first memory string;   a second line electrically coupled to the second selection transistor; and   wherein zero voltage is applied to a gate of the second selection transistor in the programming.   
     
     
       32. The method according to claim 27, wherein the non-volatile semiconductor storage device further comprising:
 word lines electrically coupled to the memory cells; and   wherein the second voltage is applied to the word lines in the programming.   
     
     
       33. The method according to claim 29, wherein the non-volatile semiconductor storage device further comprising:
 a second memory string including memory cells electrically coupled in series; and wherein either the first line or the second line electrically coupled to both the first memory string and the second memory string.   
     
     
       34. The non-volatile semiconductor storage device according to claim 21, wherein the controller is configured to perform the program operation on the condition that the program voltage is applied to the gate of the first selection transistor after a pass voltage is applied to the gate of the first selection transistor. 
     
     
       35. The method according to claim 27, wherein the programming is performed on the condition that a program voltage is applied to the gate of the first selection transistor after a pass voltage is applied to the gate of the first selection transistor.