Power conversion integrated circuit and method for programming

Abstract

A single input pin ( 48 ) provides multi-functional features for programming a power supply ( 10 ). By connecting the appropriate interface circuit ( 92, 100, or 112 ) to the single input pin ( 48 ), the power supply ( 10 ) is programmed for specific behaviors during power up and toggling of an on/off switch ( 96, 108 ). In one mode of operation a light emitting diode ( 106 ) in the interface circuit ( 100 ) is optically coupled to a microprocessor for signaling the closure of the on/off switch ( 108 ), allowing the microprocessor to control the power supply ( 10 ) through an opto-coupler ( 102 ). In another mode of operation, the single on/off switch ( 96 ) controls the power supply ( 10 ). In yet another mode of operation, Zener diode ( 118 ) in the interface circuit ( 112 ) controls the power supply ( 10 ) during brown-out and black-out conditions.

We claim: 
     
       1. A power conversion integrated circuit, comprising:
 a state circuit having an output that supplies a mode signal, wherein the state circuit includes
 a comparator having a first input coupled for receiving a control signal and a second input coupled for receiving a first reference signal, and 
 a memory circuit having a first input coupled to an output of the comparator for setting an output state of the memory circuit according to a value of the control signal; and 
   a control circuit coupled for receiving the mode signal that sets a mode of operation, where the control circuit is responsive to a feedback signal for providing a pulse-width modulated control signal.   
     
     
       2. The power conversion integrated circuit of  claim 1 , wherein the comparator includes:
 a first comparator having a first input coupled for receiving the control signal, a second input coupled for receiving the first reference signal, and an output coupled to the first input of the memory circuit; and   a second comparator having a first input coupled for receiving the control signal, a second input coupled for receiving a second reference signal, and an output coupled to a second input of the memory circuit.   
     
     
       3. The power conversion integrated circuit of  claim 2 , further including a resistor divider network for generating the first reference signal at a first output and the second reference signal at a second output. 
     
     
       4. The power conversion integrated circuit of  claim 3 , wherein the resistor divider network includes:
 a first resistor having first and second terminals, the first terminal of the first resistor coupled to a first power supply conductor;   a second resistor having first and second terminals, the first terminal of the second resistor coupled to the second terminal of the first resistor and serving as the first output of the resistor divider network; and   a third resistor having first and second terminals, the first terminal of the third resistor coupled to the second terminal of the second resistor and serving as the second output of the resistor divider network, and the second terminal of the third resistor coupled to a second power supply conductor.   
     
     
       5. The power conversion integrated circuit of  claim 4 , further including a pulse filter having an input coupled to the output of the second comparator and an output coupled to the second input of the memory circuit. 
     
     
       6. The power conversion integrated circuit of  claim 1 , wherein the memory circuit has at least one storage element for storing an operating mode of the power conversion integrated circuit. 
     
     
       7. The power conversion integrated circuit of  claim 1 , further including a reset circuit having an input coupled to a logic under voltage signal and an output coupled to the control signal. 
     
     
       8. A semiconductor chip having at least four external electrical connections, comprising:
 an internal regulator; a state circuit having an output coupled to a control input of the internal regulator;   a first electrical connection terminal for coupling an external ground reference to an internal ground reference of the internal regulator;   a second electrical connection terminal for providing a pulse-width modulated output signal from an output of the internal regulator;   a third electrical connection terminal coupled for receiving a feedback signal at an input of the internal regulator to control the pulse-width modulated output signal; and   a fourth electrical connection terminal coupled for receiving a control signal which is applied to the state circuit to set a mode of operation of the internal regulator.   
     
     
       9. The semiconductor chip of  claim 8 , further comprising a fifth electrical connection terminal coupled for receiving a bias voltage which is applied to the state circuit and to the internal regulator. 
     
     
       10. A programmable power supply, comprising:
 a transformer receiving a rectified signal at a primary side of the transformer;   a state circuit having an input and an output for setting a mode of operation of the programmable power supply, wherein the state circuit includes,
 a comparator circuit having a first input coupled to the input of the state circuit for receiving a control signal and a second input coupled for receiving a first reference signal, and 
 a memory circuit having a first input coupled to an output of the comparator for setting an output state of the memory circuit according to a value of the control signal where the output state of the memory circuit controls the mode of operation; 
   a control circuit coupled for receiving the output state of the memory circuit and wherein the control circuit is responsive to a feedback signal for providing a pulse-width modulated control signal; and   a transistor having a control terminal for receiving the pulse-width modulated control signal, a first conduction terminal coupled to the primary side of the transformer, and a second conduction terminal coupled to ground.   
     
     
       11. The programmable power supply of  claim 10 , wherein the comparator circuit includes:
 a first comparator having a first input coupled for receiving the control signal, a second input coupled for receiving the first reference signal, and an output coupled to the first input of the memory circuit; and   a second comparator having a first input coupled for receiving the control signal, a second input coupled for receiving a second reference signal, and an output coupled to a second input of the memory circuit.   
     
     
       12. The programmable power supply of  claim 10 , further including a resistor divider network for generating a first reference signal at a first output and a second reference signal at a second output. 
     
     
       13. The programmable power supply of  claim 12 , wherein the resistor divider network includes:
 a first resistor having first and second terminals, the first terminal of the first resistor coupled to a first power supply conductor;   a second resistor having first and second terminals, the first terminal of the second resistor coupled to the second terminal of the first resistor and serving as the first output of the resistor divider network; and   a third resistor having first and second terminals, the first terminal of the third resistor coupled to the second terminal of the second resistor and serving as the second output of the resistor divider network, and the second terminal of the third resistor coupled to a second power supply conductor.   
     
     
       14. A method for controlling a mode of operation of a power converter, comprising the steps of:
 controlling a pulse-width modulated output signal of the power converter in response to a feedback signal; and   setting a memory state according to a comparison between a control signal and a first reference signal where the memory state controls the mode of operation of the power converter.   
     
     
       15. The method of  claim 14 , further comprising the steps of:
 monitoring a signal at an input pin; and   maintaining a same operating state when the input pin receives a voltage about midway between an operating potential and a ground reference.   
     
     
       16. The method of  claim 14 , further comprising the steps of requesting an on-operating state when a power supply is off and an input pin receives a voltage greater than a first reference voltage. 
     
     
       17. The method of  claim 14 , further comprising the steps of requesting a toggle condition when a power supply is on and an input pin receives a voltage greater than a first reference voltage. 
     
     
       18. The method of  claim 15 , further comprising the steps of requesting that an output state be toggled when a power supply is on and an input pin receives a voltage less than a second reference voltage. 
     
     
       19. The method of  claim 14 , further comprising the step of operating in an off-operating state when a brown-out occurs that includes receiving a signal that is proportional to a line voltage that is less than a second reference voltage. 
     
     
       20. The method of  claim 14 , further comprising the step of operating in an off-operating state when a black-out occurs that includes receiving a signal that is proportional to a line voltage that is less than a second reference voltage. 
     
     
       21. A power converter circuit, comprising:
 a pulse width modulated (PWM) control circuit configured to produce a control signal at an output of the PWM control circuit in response to a feedback signal received at a first input of the PWM control circuit; and   a state circuit configured to prevent the control signal from switching only during a value of a state control signal received at an input of the state circuit, the state circuit including,
 (a) a first comparator configured to produce a first signal at an output of the first comparator based on a comparison between the state control signal and a first reference, 
 (b) a second comparator configured to produce a second signal at an output of the second comparator based on a comparison between the state control signal and a second reference, and 
 (c) a logic circuit including an output coupled to a second input of the PWM control circuit and configured to produce a mode signal at the output of the logic circuit in response to decoding the outputs of the first and second comparators and setting the PWM control circuit to a non-operational off-state to conserve energy for an extended period of time as determined by the state control signal, wherein the power converter circuit is provided in a monolithic integrated circuit package and the input of the state circuit is coupled to a pin of the monolithic integrated circuit package. 
   
     
     
       22. The power converter circuit of claim 21, wherein the mode signal takes on a logic zero value or a logic one value. 
     
     
       23. A semiconductor package, comprising:
 a first electrical connection to the semiconductor package;   a second electrical connection to the semiconductor package;   a third electrical connection to the semiconductor package;   a control circuit configured to generate a control signal at an output of the control circuit in response to a feedback signal received at the first electrical connection; and   a chip disable circuit configured to generate a mode signal that prevents the control signal of the control circuit from switching during a value of a state control signal received at the second electrical connection to the semiconductor package, the chip disable circuit including
 (a) a first comparator configured to generate a first signal at an output of the first comparator based on a comparison between the state control signal and a first reference, 
 (b) a second comparator configured to generate a second signal at an output of the second comparator based on a comparison between the state control signal and a second reference that is different from the first reference, and 
 (c) a logic circuit including an output coupled to an input of the control circuit and configured to generate the mode signal at the output of the logic circuit in response to decoding the outputs of the first and second comparators and setting the regulator circuit to a non-operational off-state. 
   
     
     
       24. The semiconductor package of claim 23, further comprising a transistor configured to generate a switching signal at the third electrical connection in response to the control signal, the transistor including a control terminal coupled to the output of the control circuit, the transistor further including a conduction terminal coupled to the third electrical connection. 
     
     
       25. The semiconductor package of claim 24, wherein the mode signal maintains the control circuit and the transistor in a non-switching state for a period of time as determined by the state control signal. 
     
     
       26. The semiconductor package of claim 23, wherein the control circuit comprises a pulse width modulator. 
     
     
       27. The semiconductor package of claim 24, wherein the transistor comprises a bipolar transistor. 
     
     
       28. The semiconductor package of claim 24, wherein the transistor comprises an insulated gate bipolar transistor. 
     
     
       29. An integrated circuit package including a power supply regulator circuit, the power supply regulator circuit comprising:
 a first comparator configured to generate a first signal at an output of the first comparator based on a comparison between a state control signal received at a pin of the integrated circuit package and a first reference, the state control signal controlling an on-state and an off-state of the power supply regulator circuit;   a second comparator configured to generate a second signal at an output of the second comparator based on a comparison between the state control signal and a second reference;   a logic circuit configured to generate a value of a mode signal at an output of the logic circuit during a first value of the first signal and a second value of the second signal; and   a control circuit configured to generate a control signal at an output of the control circuit in response to a feedback signal applied to a first input of the control circuit and the mode signal, a second input of the control circuit coupled to receive the mode signal at the output of the logic circuit, wherein the logic circuit decodes output states of the first and second comparators to set the power supply regulator circuit to the on-state or the off-state for a period of time as determined by the state control signal.   
     
     
       30. The integrated circuit package of claim 29, the power supply regulator circuit further comprising a transistor configured to generate a switching signal at an output of the power supply regulator circuit in response to the control signal, the transistor including a control terminal coupled to the output of the control circuit, the transistor further including a conduction terminal coupled to the output of the power supply regular circuit. 
     
     
       31. The integrated circuit package of claim 30, wherein the control signal is prevented from switching in response to the mode signal, thereby placing the control circuit and the transistor in a non-switching state and the power supply regulator circuit in the off-state. 
     
     
       32. The integrated circuit package of claim 31, wherein the control circuit remains in the non-switching state while the mode signal is in a first state. 
     
     
       33. The integrated circuit package of claim 29, wherein the control circuit comprises a pulse width modulator. 
     
     
       34. A method of controlling an operational state of a power conversion control circuit in a semiconductor package, comprising:
 receiving a state control signal at a pin of the semiconductor package for controlling an operational state of a power conversion control circuit;   comparing the state control signal to a first reference and to a second reference less than the first reference;   generating a first value of a mode signal during a second value of the state control signal, the first value of the mode signal being dependent upon the comparing of the state control signal to the first reference and the second reference; and   setting the operational state of the power conversion control circuit to one of a plurality of operational states in response to the mode signal depending on whether the state control signal is greater than the first reference value, or the state control signal is between the first and second reference values, or the state control signal is less than the second reference value.   
     
     
       35. The method of claim 34, wherein setting the operational state of the power conversion control circuit comprises:
 setting the operational state to a first state as a result of the state control signal being less than the second reference;   setting the operational state to a second state as a result of the state control signal being greater than the second reference but less than the first reference; and   setting the operational state to a third state as a result of the state control signal being greater than the first reference.   
     
     
       36. The method of claim 35, wherein setting the operational state to one of the first, second, or third states comprises preventing a control signal that is generated by the power conversion control circuit from switching. 
     
     
       37. The method of claim 36, wherein preventing the control signal from switching comprises preventing the control signal from transitioning from a first voltage to a second voltage in response to a feedback signal. 
     
     
       38. The method of claim 37, wherein preventing the control signal from transitioning comprises maintaining the control signal at a logic zero value. 
     
     
       39. The method of claim 37, wherein preventing the control signal from transitioning comprises maintaining the control signal at a logic one value.