Nonvolatile semiconductor memory device

Abstract

According to one embodiment, in the case of performing an operation for increasing a threshold voltage of a first transistor or a third transistor, a control circuit is configured to apply a first voltage to a bit line, and apply a second voltage greater than the first voltage to a gate of a second transistor, thereby rendering the second transistor in a conductive state to transfer the first voltage to a second semiconductor layer, and then apply a program voltage to a gate of the first transistor or the third transistor to store a charge in a second charge storage layer.

What is claimed is: 
     
       1. A nonvolatile semiconductor memory device, comprising:
 a plurality of memory strings each including a plurality of memory transistors connected in series; 
 a first transistor having one end connected to one end of one of the memory strings and functioning as a drain side select transistor of the one of the memory strings; 
 a second transistor having one end connected to the other end of the first transistor; 
 a third transistor having one end connected to the other end of the one of the memory strings and functioning as a source side select transistor of the one of the memory strings; 
 a fourth transistor having one end connected to the other end of the third transistor; 
 a bit line connected to the other end of the second transistor; 
 a source line connected to the other end of the fourth transistor; and 
 a control circuit configured to control a state of the memory strings, the first transistor, the second transistor, the third transistor, and the fourth transistor, 
 each of the memory strings comprising: 
 a first semiconductor layer including a first columnar portion extending in a perpendicular direction with respect to a substrate and functioning as a body of the memory transistors; 
 a first charge storage layer surrounding the first columnar portion and changing a threshold voltage of the memory transistors by storing a charge; and 
 a first conductive layer surrounding the first columnar portion with the first charge storage layer sandwiched therebetween, extending in parallel to the substrate, and functioning as a gate of the memory transistors, and 
 the first through fourth transistors each comprising: 
 a second semiconductor layer including a second columnar portion extending in the perpendicular direction with respect to the substrate and functioning as a body of the first through fourth transistors; 
 a second charge storage layer surrounding the second columnar portion and changing a threshold voltage of the first through fourth transistors by storing a charge; and 
 a second conductive layer surrounding the second columnar portion with the second charge storage layer sandwiched therebetween, extending in parallel to the substrate, and functioning as a gate of the first through fourth transistors, 
 wherein 
 in the case of performing an operation for increasing the threshold voltage of the first transistor or the third transistor, the control circuit is configured to apply a first voltage to the bit line, and apply a second voltage greater than the first voltage to a gate of the second transistor, thereby rendering the second transistor in a conductive state to transfer the first voltage to the second semiconductor layer, and then apply a program voltage to a gate of the first transistor or the third transistor to store a charge in the second charge storage layer, and 
 in the case of leaving the threshold voltage of the first transistor or the third transistor unincreased, the control circuit is configured to apply the second voltage to the bit line, and apply the second voltage to the gate of the second transistor, thereby charging the first semiconductor layer and the second semiconductor layer to a certain voltage from the bit line via the second transistor and subsequently render the second transistor in a non-conductive state to maintain the first semiconductor layer and the second semiconductor layer in a floating state, and then, apply the program voltage to the gate of the first transistor or the third transistor to increase a voltage of the second semiconductor layer through coupling, thereby prohibiting storage of charge in the second charge storage layer. 
 
     
     
       2. The nonvolatile semiconductor memory device according to  claim 1 , wherein
 prior to executing the operation for increasing the threshold voltage of the first transistor or the third transistor, the control circuit is configured to increase the threshold voltage of the second transistor and the fourth transistor from a negative voltage to a positive voltage. 
 
     
     
       3. The nonvolatile semiconductor memory device according to  claim 2 , wherein
 subsequent to executing the operation for increasing the threshold voltage of the first transistor or the third transistor, the control circuit is configured to change the threshold voltage of the second transistor and the fourth transistor from the positive voltage back to the negative voltage. 
 
     
     
       4. The nonvolatile semiconductor memory device according to  claim 1 , wherein
 prior to executing the operation for increasing the threshold voltage of the first transistor or the third transistor, the control circuit is configured to perform an erase operation on the first transistor and the third transistor. 
 
     
     
       5. The nonvolatile semiconductor memory device according to  claim 1 , wherein
 the control circuit is configured to perform reading of the threshold voltage of the first transistor or the third transistor, and when the threshold voltage of the first transistor or the third transistor is of a certain value or less, the control circuit is configured to execute an operation for increasing the threshold voltage of the first transistor and the third transistor. 
 
     
     
       6. The nonvolatile semiconductor memory device according to  claim 1 , wherein
 a plurality of the second semiconductor layer are disposed in a matrix in a plane parallel to the substrate and are commonly connected to the second conductive layer. 
 
     
     
       7. The nonvolatile semiconductor memory device according to  claim 6 , wherein
 the second conductive layer functioning as the gate of the third or fourth transistors is formed in a comb-tooth shape or a rectangular plate shape in the plane parallel to the substrate. 
 
     
     
       8. The nonvolatile semiconductor memory device according to  claim 1 , wherein
 the first semiconductor layer comprises a joining portion configured to join lower ends of a pair of first columnar portions. 
 
     
     
       9. The nonvolatile semiconductor memory device according to  claim 2 , wherein
 the control circuit is configured to apply a third voltage to the source line and the bit line, and apply a fourth voltage higher than the third voltage to the gates of the second transistor and the fourth transistor, thereby increasing the threshold voltage of the second transistor and the fourth transistor from the negative voltage to the positive voltage. 
 
     
     
       10. The nonvolatile semiconductor memory device according to  claim 3 , wherein
 the control circuit is configured to apply a fifth voltage to the source line and the bit line, and apply a sixth voltage lower than the fifth voltage to the gate of the second transistor or the fourth transistor, thereby changing the threshold voltage of the second transistor or the fourth transistor from the positive voltage back to the negative voltage. 
 
     
     
       11. The nonvolatile semiconductor memory device according to  claim 4 , wherein
 the control circuit is configured to apply a seventh voltage to the source line and the bit line, and apply an eighth voltage lower than the seventh voltage to the gates of the first transistor and the third transistor, thereby performing the erase operation on the first transistor and the third transistor. 
 
     
     
       12. The nonvolatile semiconductor memory device according to  claim 5 , wherein
 the control circuit is configured to apply a ninth voltage to the gates of the memory transistors, the gates of the second transistor and the fourth transistor, and any one of the gate of the first transistor or the third transistor, apply a tenth voltage lower than the ninth voltage to the others, apply an eleventh voltage to the bit line, and apply a twelfth voltage lower than the eleventh voltage to the source line, thereby reading the threshold voltage of the first transistor or the third transistor. 
 
     
     
       13. A nonvolatile semiconductor memory device, comprising:
 a plurality of memory strings each including a plurality of memory transistors connected in series; 
 a first transistor having one end connected to one end of one of the memory strings and functioning as a drain side select transistor of the one of the memory strings; 
 a second transistor having one end connected to the other end of the first transistor; 
 a third transistor having one end connected to the other end of the one of the memory strings and functioning as a source side select transistor of the one of the memory strings; 
 a fourth transistor having one end connected to the other end of the third transistor; 
 a bit line connected to the other end of the second transistor; 
 a source line connected to the other end of the fourth transistor; and 
 a control circuit configured to control a state of the memory strings, the first transistor, the second transistor, the third transistor, and the fourth transistor, 
 each of the memory strings comprising: 
 a first semiconductor layer including a first columnar portion extending in a perpendicular direction with respect to a substrate and functioning as a body of the memory transistors; 
 a first charge storage layer surrounding the first columnar portion and changing a threshold voltage of the memory transistors by storing a charge; and 
 a first conductive layer surrounding the first columnar portion with the first charge storage layer sandwiched therebetween, extending in parallel to the substrate, and functioning as a gate of the memory transistors, and 
 the first through fourth transistors each comprising: 
 a second semiconductor layer including a second columnar portion extending in the perpendicular direction with respect to the substrate and functioning as a body of the first through fourth transistors; 
 a second charge storage layer surrounding the second columnar portion and changing a threshold voltage of the first through fourth transistors by storing a charge; and 
 a second conductive layer surrounding the second columnar portion with the second charge storage layer sandwiched therebetween, extending in parallel to the substrate, and functioning as a gate of the first through fourth transistors, 
 wherein 
 prior to executing an operation for increasing the threshold voltage of the first transistor or the third transistor, the control circuit is configured to increase the threshold voltage of the second transistor and the fourth transistor from a negative voltage to a positive voltage. 
 
     
     
       14. The nonvolatile semiconductor memory device according to  claim 13 , wherein
 subsequent to executing the operation for increasing the threshold voltage of the first transistor or the third transistor, the control circuit is configured to change the threshold voltage of the second transistor and the fourth transistor from the positive voltage back to the negative voltage. 
 
     
     
       15. The nonvolatile semiconductor memory device according to  claim 13 , wherein
 prior to executing the operation for increasing the threshold voltage of the first transistor or the third transistor, the control circuit is configured to performs an erase operation on the first transistor and the third transistor. 
 
     
     
       16. The nonvolatile semiconductor memory device according to  claim 13 , wherein
 the control circuit is configured to perform reading of the threshold voltage of the first transistor or the third transistor, and when the threshold voltage of the first transistor or the third transistor is of a certain value or less, the control circuit is configured to execute an operation for increasing the threshold voltage of the first transistor and the third transistor. 
 
     
     
       17. The nonvolatile semiconductor memory device according to  claim 13 , wherein
 a plurality of the second semiconductor layer are disposed in a matrix in a plane parallel to the substrate and are commonly connected to the second conductive layer. 
 
     
     
       18. The nonvolatile semiconductor memory device according to  claim 17 , wherein
 the second conductive layer functioning as the gate of the third or fourth transistors is formed in a comb-tooth shape or a rectangular plate shape in the plane parallel to the substrate. 
 
     
     
       19. The nonvolatile semiconductor memory device according to  claim 13 , wherein
 the first semiconductor layer comprises a joining portion configured to join lower ends of a pair of first columnar portions. 
 
     
     
       20. A nonvolatile semiconductor memory device, comprising:
 a first memory unit including a plurality of memory cells coupled in series, a first selection transistor, a second selection transistor, a third selection transistor, and a fourth selection transistor, the first selection transistor and the second selection transistor being coupled in series, the third selection transistor and the fourth selection transistor being coupled in series;   a bit line coupled to the first selection transistor;   a source line electrically coupled to the fourth selection transistor; and   a controller configured to perform a first operation before a normal operation, the normal operation including a read operation, a write operation, an erase operation;   wherein the controller is configured to apply a first voltage to a gate of the second selection transistor, and a gate of the third selection transistor, then apply a program voltage to a gate of the first selection transistor and a gate of the fourth selection transistor in the first operation, the program voltage being higher than the first voltage.    
     
     
       21. The nonvolatile semiconductor memory device according to claim 20, further comprising:
 a plurality of blocks including a first block, the first block including the first memory unit,   wherein the controller is configured to perform the first operation when the first block is selected.    
     
     
       22. The nonvolatile semiconductor memory device according to claim 21, further comprising:
 a second memory unit including a plurality of memory cells coupled in series, a fifth selection transistor, a sixth selection transistor, a seventh selection transistor, and an eighth selection transistor, the fifth selection transistor and the sixth selection transistor being coupled in series, the seventh selection transistor and the eighth selection transistor being coupled in series.    
     
     
       23. The nonvolatile semiconductor memory device according to claim 22, further comprising:
 a plurality of blocks including a first block and a second block, the first block including the first memory unit, the second block including a second memory unit,   wherein the controller is configured to perform the first operation to the first memory unit when the first block is selected.    
     
     
       24. The nonvolatile semiconductor memory device according to claim 23, further comprising:
 a third memory unit including a plurality of memory cells coupled in series,   wherein the first memory unit and the third memory unit is in the first block, and gates of the memory cells in the first memory unit are electrically coupled to gates of the memory cells in the third memory unit.    
     
     
       25. A nonvolatile semiconductor memory device, comprising:
 a first memory unit including a plurality of memory cells coupled in series, a first selection transistor, a second selection transistor, a third selection transistor, and a fourth selection transistor, the first selection transistor and the second selection transistor being coupled in series, the third selection transistor and the fourth selection transistor being coupled in series;   a bit line coupled to the first selection transistor;   a source line electrically coupled to the fourth selection transistor; and   a controller configured to perform a first operation or a second operation before a normal operation, the normal operation including a read operation, a write operation, an erase operation;   wherein the controller is configured to apply a first voltage to a bit line, apply a second voltage to a gate of the second selection transistor, and a gate of the third selection transistor, then apply a program voltage to a gate of the first selection transistor and a gate of the fourth selection transistor in the first operation, the program voltage being higher than the first voltage,   wherein the controller is configured to apply a third voltage higher than the first voltage to a bit line, apply a fourth voltage to a gate of the second selection transistor, and a gate of the third selection transistor, then apply a program voltage to a gate of the first selection transistor and a gate of the third selection transistor in the second operation.    
     
     
       26. The nonvolatile semiconductor memory device according to claim 25, further comprising:
 a plurality of blocks including a first block, the first block including the first memory unit,   wherein the controller is configured to perform the first operation when the first block is selected.    
     
     
       27. The nonvolatile semiconductor memory device according to claim 26, further comprising:
 a second memory unit including a plurality of memory cells coupled in series, a fifth selection transistor, a sixth selection transistor, a seventh selection transistor, and an eighth selection transistor, the fifth selection transistor and the sixth selection transistor being coupled in series, the seventh selection transistor and the eighth selection transistor being coupled in series.    
     
     
       28. The nonvolatile semiconductor memory device according to claim 27, further comprising:
 a plurality of blocks including a first block and a second block, the first block including the first memory unit, the second block including a second memory unit,   wherein the controller is configured to perform the first operation to the first memory unit when the first block is selected.    
     
     
       29. The nonvolatile semiconductor memory device according to claim 28, further comprising:
 a third memory unit including a plurality of memory cells coupled in series,   wherein the first memory unit and the third memory unit is in the first block, and gates of the memory cells in the first memory unit are electrically coupled to gates of the memory cells in the third memory unit.