Three-dimensionally stacked nonvolatile semiconductor memory

Abstract

A three-dimensionally stacked nonvolatile semiconductor memory of an aspect of the present invention including conductive layers stacked on a semiconductor substrate in such a manner as to be insulated from one another, a bit line which is disposed on the stacked conductive layers, a semiconductor column which extends through the stacked conductive layers, word lines for which the stacked conductive layers except for the uppermost and lowermost conductive layers are used and which have a plate-like planar shape, memory cells provided at intersections of the word lines and the semiconductor column, a register circuit which has information to supply a potential suitable for each of the word lines, and a potential control circuit which reads the information retained in the register circuit in accordance with an input address signal of a word line and which supplies a potential suitable for the word line corresponding to the address signal.

What is claimed is: 
     
       1. A three-dimensionally stacked nonvolatile semiconductor memory comprising:
 a memory cell array provided in a semiconductor substrate; 
 conductive layers stacked above the semiconductor substrate in the memory cell array in such a manner as to be insulated from one mother; 
 a bit line which is disposed above the conductive layers in such a manner as to be insulated from the conductive layers; 
 a semiconductor column which extends through the conductive layers and which has an upper end connected to the bit line and a lower end connected to the semiconductor substrate; 
 word lines for which the conductive layers except for the uppermost and lowermost conductive layers are used; 
 memory cells provided at intersections of word lines and the semiconductor column, respectively; 
 a register circuit which retains operation setting information for the memory cell array and which has information to supply a potential suitable for each of the word lines; and 
 a potential control circuit which controls the potentials supplied to the word lines and which reads the information retained in the register circuit in accordance with a position of a word line in a direction perpendicular to the surface of the semiconductor substrate and which supplies a potential suitable for the word line corresponding to an input address signal. 
 
     
     
       2. The three-dimensionally stacked nonvolatile semiconductor memory according to  claim 1 , wherein
 the register circuit has registers which retain potential codes indicating the potentials suitable for the word lines, respectively, and 
 the potential control circuit selects the potential code corresponding to the input address signal from registers, and supplies the suitable potential to the word line corresponding to the input address signal in accordance with the selected potential code. 
 
     
     
       3. The three-dimensionally stacked nonvolatile semiconductor memory according to  claim 1 , wherein
 the register circuit has 
 a first register which retains, as a reference code, a value indicating the potential suitable for one of the word lines, and 
 one or more second registers which are respectively provided to correspond to the remaining word lines except for the one word line corresponding to the reference code and which retain a difference code between the reference code and a value indicating the potential suitable for each of the remaining word lines; and 
 the potential control circuit selects the difference code corresponding to the input address signal from the one or more second registers, and supplies the suitable potential to a word line corresponding to the input address signal in accordance with a calculation result obtained from the selected difference code and the reference code. 
 
     
     
       4. The three-dimensionally stacked nonvolatile semiconductor memory according to  claim 1 , wherein
 the register circuit has first and second registers which retain first and second coefficients of an approximation function, respectively, and 
 the potential control circuit uses the input address signal as a variable of the approximation function, and supplies the suitable potential to the word line corresponding to the input address signal in accordance with the approximation function using the first and second coefficients. 
 
     
     
       5. The three-dimensionally stacked nonvolatile semiconductor memory according to  claim 1 , further comprising:
 an external device which externally controls the operation of the memory cell array, 
 wherein the potential suitable for each of the word lines is set by an instruction from the external device. 
 
     
     
       6. The three-dimensionally stacked nonvolatile semiconductor memory according to  claim 1 , wherein
 the potential control circuit has 
 an arithmetic unit which outputs a value indicating the potential supplied to the one word line in accordance with an output of the register circuit and the address signal, 
 a converter which outputs a converted value of the value indicating the potential supplied to the one word line, 
 a comparator which outputs a comparison value between a reference value and the converted value, and 
 a potential generator which generates a potential suitable for each of the word lines in accordance with the comparison value. 
 
     
     
       7. The three-dimensionally stacked nonvolatile semiconductor memory according to  claim 1 , wherein
 the uppermost conductive layer is a straight first select gate line extending in a second direction intersecting with a first direction, and 
 the lowermost conductive layer is a plate-like second select gate line. 
 
     
     
       8. The three-dimensionally stacked nonvolatile semiconductor memory according to  claim 1 , wherein
 the potential supplied to upper one of word lines is equal to or more than the potential supplied to lower one of the word lines. 
 
     
     
       9. The three-dimensionally stacked nonvolatile semiconductor memory according to  claim 1 , wherein
 the memory cell has an insulating film functioning as a charge storage layer. 
 
     
     
       10. The three-dimensionally stacked nonvolatile semiconductor memory according to  claim 3 , wherein
 the number of bits indicating the difference value in each of the second registor register is smaller than the number of bits indicating the reference value in the first registor register. 
 
     
     
       11. The three-dimensionally stacked nonvolatile semiconductor memory according to  claim 3 , wherein the difference code using writing operation differs from the difference code using reading operation. 
     
     
       12. The three-dimensionally stacked nonvolatile semiconductor memory according to  claim 1 , wherein
 at least one of the operation setting information and the information to supply a potential suitable for each of the word lines includes adjusted values in each of the word lines to supply the potential suitable for the word line, and the adjusted values are determined based on arithmetic processing for driving results of each of the word lines. 
 
     
     
       13. A semiconductor memory comprising:
 a memory string including a first memory cell and a second memory cell, the first memory cell being above a semiconductor substrate, the second memory cell being above the first memory cell;   a first word line electrically connected to a gate of the first memory cell;   a second word line electrically connected to a gate of the second memory cell;   a control circuit configured to perform a program operation on the condition that a first program voltage is applied to the first word line when the first word line is selected, a second program voltage is applied to the second word line when the second word line is selected and the first program voltage is different from the second program voltage.    
     
     
       14. The semiconductor memory according to claim 13, wherein
 the first program voltage is lower than the second program voltage.    
     
     
       15. The semiconductor memory according to claim 13, wherein
 the memory string includes   a semiconductor column extending in a first direction perpendicular to the semiconductor substrate;   a first conductive layer disposed above the semiconductor substrate;   a second conductive layer disposed above the first conductive layer; and   a charge storage material disposed between the first conductive layer and the semiconductor column.    
     
     
       16. The semiconductor memory according to claim 15, wherein
 a diameter of the semiconductor column corresponding to the second conductive layer is larger than a diameter of the semiconductor column corresponding to the first conductive layer.    
     
     
       17. The semiconductor memory according to claim 13, wherein
 the control circuit is configured to perform a program operation on the condition that a first pass voltage is applied to the first word line when the second word line is selected, a second pass voltage is applied to the second word line when the first word line is selected and the first pass voltage is lower than the second pass voltage.    
     
     
       18. The semiconductor memory according to claim 16, wherein
 the control circuit is configured to perform a program operation on the condition that a first pass voltage is applied to the first word line when the second word line is selected, a second pass voltage is applied to the second word line when the first word line is selected and the first pass voltage is lower than the second pass voltage.    
     
     
       19. The semiconductor memory according to claim 13, wherein
 the control circuit is configured to perform a read operation on the condition that a first read un-selection voltage is applied to the first word line when the second word line is selected, a second read un-selection voltage is applied to the second word line when the first word line is selected and the first read un-selection voltage is different from the second read un-selection voltage.    
     
     
       20. The semiconductor memory according to claim 16, wherein
 the control circuit is configured to perform a read operation on the condition that a first read un-selection voltage is applied to the first word line when the second word line is selected, a second read un-selection voltage is applied to the second word line when the first word line is selected and the first read un-selection voltage is different from the second read un-selection voltage.