System-on-chip with master/slave debug interface

Abstract

A System-on-Chip (SOC) debugging system comprising a plurality of SOCs connected to a shared bus, at least one of the plurality of SOCs being a master SOC and comprising a master/slave debug interface, wherein the master/slave debug interface is a bidirectional debug interface configured to initiate transactions on the shared bus and operable to send and receive debug data between the SOCs, wherein the debug data comprises trace data.

What is claimed is: 
     
       1. A System-on-Chip (SOC) debugging system comprising a plurality of SOCs connected to a shared bus, at least one of the plurality of SOCs being a master SOC and comprising a master/slave bidirectional debug interface operable in a first mode as a slave and in a second mode as a master, and wherein the master/slave debug interface is a bidirectional debug interface configured to initiate transactions on the shared bus and operable to send and receive debug data between the SOCs, wherein the debug data comprises trace data. 
     
     
       2. The SOC debugging system of  claim 1 , wherein the master SOC comprises a user interface. 
     
     
       3. The SOC debugging system of  claim 2 , wherein the user interface is a USB interface. 
     
     
       4. The SOC debugging system of  claim 2 , wherein the user interface is a network interface. 
     
     
       5. The SOC debugging system of  claim 2 , wherein the user interface is a wireless interface. 
     
     
       6. The SOC debugging system of  claim 1 , wherein the transactions include instructions to store data in memories of the SOCs, and to read data from the memories of the SOCs. 
     
     
       7. The SOC debugging system of  claim 6 , wherein the master SOC comprises a user interface, and the transactions further include instructions to transfer data to and from a host system via the user interface. 
     
     
       8. The SOC debugging system of  claim 1 , wherein the master/slave debug interface is a two pin debug interface including one pin for a clock signal and another pin for bidirectional data. 
     
     
       9. The SOC debugging system of  claim 1 , wherein the at least one master SOC can be configured to function as a tool hardware front-end for the shared debug bus. 
     
     
       10. The SOC debugging system of  claim 1 , wherein the at least one master SOC functions as a bus bridge between a host system and the shared debug bus. 
     
     
       11. The SOC debugging system of claim  1  2, wherein the at least one master SOC is connected to a host system through the user interface and accesses the non-master SOCs indirectly through the at least one master SOC. 
     
     
       12. The SOC debugging system of  claim 1 , wherein the at least one master SOC includes software acting as a debug monitor. 
     
     
       13. The SOC debugging system of  claim 1 , wherein the at least one master SOC includes a trace buffer for capturing traces from the other SOCs. 
     
     
       14. A method for debugging a System-on-Chip (SOC) integrated circuit, the method comprising:
 transmitting debug data by a bidirectional debug interface of a master SOC over a shared bus between the master SOC and at least one slave SOC; and   transmitting the debug data by a user interface of the master SOC between the master SOC and an external system coupled to the user interface of the master SOC,   wherein the bidirectional debug interface of the master SOC is operable in a default mode as a slave bidirectional debug interface and in a non-default mode as a master bidirectional debug interface.    
     
     
       15. The method of claim 14, wherein the bidirectional debug interface of the master SOC operates in the non-default mode as the master bidirectional debug interface by controlling a slave debug interface of the at least one slave SOC.  
     
     
       16. The method of claim 14, wherein the bidirectional debug interface of the master SOC operates in the default mode as the slave bidirectional debug interface by being controlled from a debug tool located external to the SOC integrated circuit.  
     
     
       17. The method of claim 14, wherein the user interface of the master SOC is a USB interface.  
     
     
       18. The method of claim 14, wherein the user interface of the master SOC is a network interface.  
     
     
       19. The method of claim 14, wherein the user interface of the master SOC is a wireless interface.  
     
     
       20. The method of claim 14, further comprising initiating instructions on the shared bus by the bidirectional debug interface of the master SOC to store data in a memory of the at least one slave SOC, and to read data from the memory of the at least one SOC.  
     
     
       21. The method of claim 14, wherein the bidirectional debug interface of the master SOC is a two pin debug interface including one pin for a clock signal and another pin for bidirectional data.  
     
     
       22. The method of claim 21, wherein the bidirectional debug interface of the master SOC operates in the non-default mode as the master bidirectional debug interface by controlling a slave debug interface of the at least one slave SOC, and wherein the clock signal is output from the master SOC to the at least one slave SOC via the one pin for the clock signal.  
     
     
       23. The method of claim 14, wherein the master SOC functions as a bus bridge between the external system and the shared bus.  
     
     
       24. The method claim 14, wherein the external system accesses the at least one slave SOC indirectly through the master SOC.  
     
     
       25. The method of claim 14, wherein the master SOC includes a debug monitor.  
     
     
       26. The method of claim 25, wherein the debug monitor performs a method comprising:
 analyzing a request received by the user interface of the master SOC from the external system;   scheduling transfer of the debug data over the shared bus from the at least one slave SOC to the bidirectional debug interface of the master SOC; and   transmitting the debug data received from the at least one slave SOC via the user interface of the master SOC to the external system.    
     
     
       27. The method claim 14, further comprising capturing trace data from the at least one slave SOC by a trace buffer of the master SOC, wherein the debug data comprises the trace data.  
     
     
       28. The method of claim 14, further comprising the storing debug data in a memory of the master SOC.  
     
     
       29. The method of claim 27, further comprising:
 transferring the trace data from the trace buffer via the user interface of the master SOC to the external system; and   analyzing the trace data by the external system.    
     
     
       30. The method of claim 14, further comprising transmitting the debug data by the bidirectional debug interface of the master SOC over the shared bus between the master SOC and a plurality of slave SOCs.  
     
     
       31. The method of claim 14, wherein the debug data comprises trace data, debug control signals, and status data.