Nonvolatile semiconductor storage device and method for operating same

Abstract

A nonvolatile semiconductor memory device for suppressing a current consumption caused by a transient current because of the potential change of the bit and word lines at the time of shifting between the programming, reading, and erasing actions in a highly integrated memory cell array is provided. A memory cell ( 1 ) array comprises two-terminal memory cells each having a variable resistance element whose resistance value reversibly changes by pulse application are arranged in a row and column directions, wherein the memory cells in a row are connected at one end to common word lines (WL 1 to WLn), the memory cells in a column are connected at the other end to common bit lines (BL 1 to BLm), and a common unselected voltage V WE /2 is applied to both unselected word and bit lines not connected to the selected memory cell during the reading, programming, and erasing actions for the selected memory cell.

The invention claimed is: 
     
       1. A nonvolatile semiconductor memory device comprising:
 a memory cell array comprising including two-terminal memory cells each comprising a variable resistance element having a resistance value reversibly changed by electric pulse application, the memory cells being arranged in a row direction and column direction such that one end of each memory cell in the same row is connected to a common word line and the other end of each memory cell in the same column is connected to a common bit line; 
 a memory cell selecting circuit selecting the configured to select a memory cell from the memory cell array by the row, column or or column of the memory cell array; 
 a voltage switch circuit applying configured to apply a voltage required for each of a plurality of memory actions including a reading action, a programming action and an erasing action in the memory cell selected by the memory cell selecting circuit, to a selected word line and a selected bit line connected to a the selected memory cell and to unselected word lines and unselected bit lines other than the above selected word line and selected bit line among word lines and bit lines, according to the memory actions; and 
 a reading circuit reading configured to read information stored in the selected memory cell to be read in the selected memory cells by detecting the an amount of a reading current flowing according to the resistance value of the variable resistance element in the selected memory cell to be read, 
 wherein the voltage switch circuit applies is further configured to:
 apply a common unselect voltage to both the unselected word lines and the unselected bit lines during each of the reading, actions; 
 apply the common unselect voltage to both the unselected word lines and the unselected bit lines during the programming actions; and 
 apply the common unselect voltage to both the unselected word lines and the unselected bit lines during the erasing actions, wherein the common unselect voltage has an absolute value greater than zero. 
 
 
     
     
       2. A nonvolatile semiconductor memory device comprising:
 a memory cell array comprising including two-terminal memory cells each comprising a variable resistance element having a resistance value reversibly changed by electric pulse application, the memory cells being arranged in a row direction and column direction such that one end of each memory cell in the same row is connected to a common word line and the other end of each memory cell in the same column is connected to a common bit line; 
 a memory cell selecting circuit configured to select a memory cell by selecting the memory cell from the memory cell array by the row, column or column of the memory cell array; 
 a voltage switch circuit applying configured to apply a voltage required for each of a plurality of memory actions including a reading action, a programming action and an erasing action in the memory cell selected by the memory cell selecting circuit, to a selected word line and a selected bit line connected to a the selected memory cell and to unselected word lines and unselected bit lines other than the above selected word line and selected bit line among word lines and bit lines, according to the memory actions; and 
 a reading circuit reading configured to read information stored in the selected memory cell to be read in the selected memory cells by detecting the an amount of a reading current flowing according to the resistance value of the variable resistance element in the selected memory cell to be read, 
 wherein the voltage switch circuit applies is further configured to:
 apply a common unselect voltage to one of the unselected word lines and the unselected bit lines at least during each of the reading actions and the programming actions, and applies to apply the common unselect voltage to the other of the unselected word lines and the unselected bit lines at least during each of the reading actions and the erasing actions, or 
 apply the common unselect voltage to the unselected bit lines during the reading actions and the programming actions and to apply the common unselect voltage to the unselected word lines during the reading actions and the erasing actions, and wherein the common unselect voltage has an absolute value greater than zero. 
 
 
     
     
       3. The nonvolatile semiconductor memory device according to  claim 1 , wherein the voltage switch circuit applies is further configured to apply the common unselect voltage to at least the unselected word lines and the unselected bit lines during each of action preparing periods just before the reading, programming and erasing actions. 
     
     
       4. The nonvolatile semiconductor memory device according to  claim 3 , wherein
 the common unselect voltage is applied to the selected word line and the selected bit line during each of the action preparing periods. 
 
     
     
       5. The nonvolatile semiconductor memory device according to  claim 1 , wherein
 the voltage switch circuit applies the common unselect voltage to one of the selected word line and the selected bit line and both of the unselected word lines and the unselected bit lines and applies a first reading voltage different from the unselect voltage to the other of the selected word line and the selected bit line, during the reading action, and 
 wherein the absolute value of voltage difference between the first reading voltage and the unselect voltage is a predetermined reading voltage lower than the lower limit value of absolute values of a programming voltage required for the programming action for the variable resistance element and an erasing voltage required for the erasing action for the variable resistance element. 
 
     
     
       6. The nonvolatile semiconductor memory device according to  claim 1 , wherein
 the voltage switch circuit applies is further configured to apply a first programming voltage higher than the common unselect voltage to one of the selected word line and the selected bit line and applies a second programming voltage lower than the common unselect voltage to the other of the selected word line and the selected bit line during the programming action, and 
 wherein the absolute value of voltage difference between the first programming voltage and the second programming voltage is a programming voltage required for the programming action for the variable resistance element. 
 
     
     
       7. The nonvolatile semiconductor memory device according to  claim 1 , wherein
 the voltage switch circuit applies is further configured to apply a first erasing voltage higher than the common unselect voltage to one of the selected word line and selected bit line and applies a second erasing voltage lower than the common unselect voltage to the other of the selected word line and the selected bit line during the erasing action, and 
 wherein the absolute value of voltage difference between the first erasing voltage and the second erasing voltage is an erasing voltage required for the erasing action for the variable resistance element. 
 
     
     
       8. The nonvolatile semiconductor memory device according to  claim 1 , wherein
 the voltage switch circuit applies is further configured to apply a first programming voltage higher than the common unselect voltage to one of the selected word line and selected bit line and applies a second programming voltage lower than the common unselect voltage to the other of the selected word line and the selected bit line during the programming action, and applies a first erasing voltage higher than the common unselect voltage to the other of the selected word line and selected bit line and applies a second erasing voltage lower than the common unselect voltage to one of the selected word line and the selected bit line during the erasing action, 
 wherein the absolute value of voltage difference between the first programming voltage and the second programming voltage is a programming voltage required for the programming action for the variable resistance element, and the absolute value of voltage difference between the first erasing voltage and the second erasing voltage is an erasing voltage required for the erasing action for the variable resistance element, and 
 wherein the first programming voltage is equal to the first erasing voltage and the second programming voltage is equal to the second erasing voltage. 
 
     
     
       9. The nonvolatile semiconductor memory device according to  claim 1 , wherein
 a voltage applied to the selected word line or the selected bit line during both of the programming and erasing actions is the ground voltage, and 
 wherein the common unselect voltage is half of a programming voltage required for the programming action for the variable resistance element or an erasing voltage required for the erasing action for the variable resistance element. 
 
     
     
       10. The nonvolatile semiconductor memory device according to  claim 1 , wherein
 a voltage applied to the selected word line or the selected bit line during both of the programming and erasing actions is the ground voltage, and   the unselect voltage is one third of a programming voltage required for the programming action for the variable resistance element or an erasing voltage required for the erasing action for the variable resistance element.   
     
     
       11. The nonvolatile semiconductor memory device according to  claim 1 , wherein
 a voltage applied to the selected word line or the selected bit line during both of the programming and erasing actions is the ground voltage, and   the unselect voltage is two thirds of a programming voltage required for the programming action for the variable resistance element or an erasing voltage required for the erasing action for the variable resistance element.   
     
     
       12. The nonvolatile semiconductor memory device according to  claim 1 , wherein
 a polarity of one of voltages applied to the selected word line and the selected bit line is positive and a polarity of the other thereof is negative during both of the programming and erasing actions, and the absolute values of them is the same, and the unselect voltage is the ground voltage.   
     
     
       13. The nonvolatile semiconductor memory device according to  claim 1 , wherein
 the voltage switch circuit applies is further configured to apply the common unselect voltage to the selected word line, selected bit line, unselected word lines and unselected bit lines in a standby state in which none of the reading, programming and erasing actions is performed. 
 
     
     
       14. The nonvolatile semiconductor memory device according to  claim 1 , wherein
 the material of the variable resistance element is comprises a metal oxide. 
 
     
     
       15. The nonvolatile semiconductor memory device according to claim  1  14, wherein
 the metal oxide as the material of the variable resistance element is comprises a transition metal oxide. 
 
     
     
       16. The nonvolatile semiconductor memory device according to claim  1  14, wherein
 the metal oxide as the material of the variable resistance element contains comprises Pr and Mn. 
 
     
     
       17. An operating method in a nonvolatile semiconductor memory device comprising a memory cell array comprising including two-terminal memory cells each comprising a variable resistance element having a resistance value reversibly changed by electric pulse application, the memory cells being arranged in a row direction and column direction such that one end of each memory cell in the same row is connected to a common word line and the other end of each memory cell in the same column is connected to a common bit line, for a plurality of memory actions including a reading action, a programming action and an erasing action in a selected memory cell selected from the memory cell array by the row, or column, or memory cell of the memory cell array, the operating method comprising:
 applying a common unselect voltage to both of unselected word lines and unselected bit lines that are not connected to the selected memory cell among word lines and bit lines during each of the reading, programming and erasing actions.; 
 applying the common unselect voltage to both the unselected word lines and the unselected bit lines during the programming actions; and 
 applying the common unselect voltage to both the unselected word lines and the unselected bit lines during the erasing actions, wherein the common unselect voltage has an absolute value greater than zero. 
 
     
     
       18. An operating method in a nonvolatile semiconductor memory device comprising a memory cell array comprising including two-terminal memory cells each comprising a variable resistance element having a resistance value reversibly changed by electric pulse application, the memory cells being arranged in a row direction and column direction such that one end of each memory cell in the same row is connected to a common word line and the other end of each memory cell in the same column is connected to a common bit line, for a plurality of memory actions including a reading action, a programming action and an erasing action in a selected memory cell selected from the memory cell array by the row, or column, or memory cell of the memory cell array, the operating method comprising:
 applying a common unselect voltage to one of unselected word lines and unselected bit lines that are not connected to the selected memory cell among word lines and bit lines at least during each of the reading actions and the programming actions, and to apply the common unselect voltage to the other of the unselected word lines and the unselected bit lines at least that are not connected to the selected memory cell among bit lines during each of the reading actions and the erasing actions, or 
 applying the common unselect voltage to the unselected bit lines during the reading actions and the programming actions and to apply the common unselect voltage to the unselected word lines during the reading actions and the erasing actions, wherein the common unselect voltage has an absolute value greater than zero. 
 
     
     
       19. The operating method of the nonvolatile semiconductor memory device according to  claim 17  comprising:
 applying the common unselect voltage to the unselected word lines and the unselected bit lines during each of action preparing periods just before the reading, programming and erasing actions. 
 
     
     
       20. The operating method of the nonvolatile semiconductor memory device according to  claim 19  comprising:
 applying the common unselect voltage to a selected word line and a selected bit line connected to the selected memory cell among the word lines and bit lines during each of the action preparing periods. 
 
     
     
       21. The operating method of the nonvolatile semiconductor memory device according to  claim 17  comprising:
 applying the common unselect voltage to one of a selected word line and a selected bit line connected to the selected memory cell and both of the unselected word lines and the unselected bit lines and a first reading voltage different from the unselect voltage to the other of the selected word line and the selected bit line, among the word lines and bit lines, during the reading action, wherein 
 the absolute value of voltage difference between the first reading voltage and the common unselect voltage is a predetermined reading voltage lower than the lower limit value of absolute values of a programming voltage required for the programming action for the variable resistance element and an erasing voltage required for the erasing action for the variable resistance element. 
 
     
     
       22. The operating method of the nonvolatile semiconductor memory device according to  claim 17 , wherein
 a voltage applied to one of a selected word line and a selected bit line connected to the selected memory cell among the word lines and the bit lines during both of the programming and erasing actions is the ground voltage, and 
 wherein the common unselect voltage is half of a programming voltage required for the programming action for the variable resistance element or an erasing voltage required for the erasing action for the variable resistance element. 
 
     
     
       23. The operating method of the nonvolatile semiconductor memory device according to  claim 17 , wherein
 a voltage applied to one of a selected word line and a selected bit line connected to the selected memory cell among the word lines and the bit lines during both of the programming and erasing actions is the ground voltage, and   the unselect voltage is one third of a programming voltage required for the programming action for the variable resistance element or an erasing voltage required for the erasing action for the variable resistance element.   
     
     
       24. The operating method of the nonvolatile semiconductor memory device according to  claim 17 , wherein
 a voltage applied to one of a selected word line and a selected bit line connected to the selected memory cell among the word lines and the bit lines during both of the programming and erasing actions is the ground voltage, and   the unselect voltage is two thirds of a programming voltage required for the programming action for the variable resistance element or an erasing voltage required for the erasing action for the variable resistance element.   
     
     
       25. The operating method of the nonvolatile semiconductor memory device according to  claim 17 , wherein
 a polarity of one of voltages applied to a selected word line and a selected bit line connected to the selected memory cell among the word lines and the bit lines during both of the programming and erasing actions is positive and a polarity of the other thereof is negative, and the absolute values of them is the same, and the unselect voltage is the ground voltage.   
     
     
       26. The operating method of the nonvolatile semiconductor memory device according to  claim 17 , wherein
 the voltage switch circuit applies the common unselect voltage to a selected word line and selected bit line connected to the selected memory cell, and the unselected word lines and unselected bit lines among the word lines and bit lines in a standby state in which none of the reading, programming, and erasing actions is performed. 
 
     
     
       27. The operating method of the nonvolatile semiconductor memory device according to  claim 17 , wherein
 the material of the variable resistance element is comprises a metal oxide. 
 
     
     
       28. The operating method of the nonvolatile semiconductor memory device according to claim  17  27, wherein
 the metal oxide as the material of the variable resistance element is comprises a transition metal oxide. 
 
     
     
       29. The operating method of the nonvolatile semiconductor memory device according to claim  17  27, wherein
 the metal oxide as the material of the variable resistance element contains comprises Pr and Mn. 
 
     
     
       30. The nonvolatile semiconductor memory device according to  claim 2 , wherein
 the voltage switch circuit applies is further configured to apply the common unselect voltage to at least the unselected word lines and the unselected bit lines during each of action preparing periods just before the reading, programming and erasing actions. 
 
     
     
       31. The nonvolatile semiconductor memory device according to  claim 2 , wherein
 the voltage switch circuit applies is further configured to apply the common unselect voltage to one of the selected word line and the selected bit line and both of the unselected word lines and the unselected bit lines and applies a first reading voltage different from the common unselect voltage to the other of the selected word line and the selected bit line, during the reading action, and 
 wherein the absolute value of voltage difference between the first reading voltage and the common unselect voltage is a predetermined reading voltage lower than the lower limit value of absolute values of a programming voltage required for the programming action for the variable resistance element and an erasing voltage required for the erasing action for the variable resistance element. 
 
     
     
       32. The nonvolatile semiconductor memory device according to  claim 2 , wherein
 the voltage switch circuit applies is further configured to apply a first programming voltage higher than the common unselect voltage to one of the selected word line and the selected bit line and applies a second programming voltage lower than the common unselect voltage to the other of the selected word line and the selected bit line during the programming action, and 
 wherein the absolute value of voltage difference between the first programming voltage and the second programming voltage is a programming voltage required for the programming action for the variable resistance element. 
 
     
     
       33. The nonvolatile semiconductor memory device according to  claim 2 , wherein
 the voltage switch circuit applies is further configured to apply a first erasing voltage higher than the common unselect voltage to one of the selected word line and selected bit line and applies a second erasing voltage lower than the common unselect voltage to the other of the selected word line and the selected bit line during the erasing action, and 
 wherein the absolute value of voltage difference between the first erasing voltage and the second erasing voltage is an erasing voltage required for the erasing action for the variable resistance element. 
 
     
     
       34. The nonvolatile semiconductor memory device according to  claim 2 , wherein
 the voltage switch circuit applies is further configured to apply a first programming voltage higher than the common unselect voltage to one of the selected word line and selected bit line and applies a second programming voltage lower than the common unselect voltage to the other of the selected word line and the selected bit line during the programming action, and applies a first erasing voltage higher than the common unselect voltage to the other of the selected word line and selected bit line and applies a second erasing voltage lower than the common unselect voltage to one of the selected word line and the selected bit line during the erasing action, 
 wherein the absolute value of voltage difference between the first programming voltage and the second programming voltage is a programming voltage required for the programming action for the variable resistance element, and the absolute value of voltage difference between the first erasing voltage and the second erasing voltage is an erasing voltage required for the erasing action for the variable resistance element, and 
 wherein the first programming voltage is equal to the first erasing voltage and the second programming voltage is equal to the second erasing voltage. 
 
     
     
       35. The nonvolatile semiconductor memory device according to  claim 2 , wherein
 a voltage applied to the selected word line or the selected bit line during both of the programming and erasing actions is the ground voltage, and 
 wherein the common unselect voltage is half of a programming voltage required for the programming action for the variable resistance element or an erasing voltage required for the erasing action for the variable resistance element. 
 
     
     
       36. The nonvolatile semiconductor memory device according to  claim 2 , wherein
 a voltage applied to the selected word line or the selected bit line during both of the programming and erasing actions is the ground voltage, and 
 wherein the common unselect voltage is one third of a programming voltage required for the programming action for the variable resistance element or an erasing voltage required for the erasing action for the variable resistance element. 
 
     
     
       37. The nonvolatile semiconductor memory device according to  claim 2 , wherein
 a voltage applied to the selected word line or the selected bit line during both of the programming and erasing actions is the ground voltage, and 
 wherein the common unselect voltage is two thirds of a programming voltage required for the programming action for the variable resistance element or an erasing voltage required for the erasing action for the variable resistance element. 
 
     
     
       38. The nonvolatile semiconductor memory device according to  claim 2 , wherein
 a polarity of one of voltages applied to the selected word line and the selected bit line is positive and a polarity of the other thereof is negative during both of the programming and erasing actions, and the absolute values of them is the same, and the unselect voltage is the ground voltage.   
     
     
       39. The nonvolatile semiconductor memory device according to  claim 2 , wherein
 the voltage switch circuit applies is further configured to apply the common unselect voltage to the selected word line, selected bit line, unselected word lines and unselected bit lines in a standby state in which none of the reading, programming and erasing actions is performed. 
 
     
     
       40. The nonvolatile semiconductor memory device according to  claim 2 , wherein
 the material of the variable resistance element is comprises a metal oxide. 
 
     
     
       41. The nonvolatile semiconductor memory device according to claim  2  40, wherein
 the metal oxide as the material of the variable resistance element is comprises a transition metal oxide. 
 
     
     
       42. The nonvolatile semiconductor memory device according to claim  2  40, wherein
 the metal oxide as the material of the variable resistance element contains comprises Pr and Mn. 
 
     
     
       43. The operating method of the nonvolatile semiconductor memory device according to  claim 18  comprising:
 applying the common unselect voltage to the unselected word lines and the unselected bit lines during each of action preparing periods just before the reading, programming and erasing actions. 
 
     
     
       44. The operating method of the nonvolatile semiconductor memory device according to  claim 18  comprising:
 applying the common unselect voltage to one of a selected word line and a selected bit line connected to the selected memory cell and both of the unselected word lines and the unselected bit lines and a first reading voltage different from the common unselect voltage to the other of the selected word line and the selected bit line, among the word lines and bit lines, during the reading action, wherein 
 the absolute value of voltage difference between the first reading voltage and the common unselect voltage is a predetermined reading voltage lower than the lower limit value of absolute values of a programming voltage required for the programming action for the variable resistance element and an erasing voltage required for the erasing action for the variable resistance element. 
 
     
     
       45. The operating method of the nonvolatile semiconductor memory device according to  claim 18 , wherein
 a voltage applied to one of a selected word line and a selected bit line connected to the selected memory cell among the word lines and the bit lines during both of the programming and erasing actions is the ground voltage, and 
 wherein the common unselect voltage is half of a programming voltage required for the programming action for the variable resistance element or an erasing voltage required for the erasing action for the variable resistance element. 
 
     
     
       46. The operating method of the nonvolatile semiconductor memory device according to  claim 18 , wherein
 a voltage applied to one of a selected word line and a selected bit line connected to the selected memory cell among the word lines and the bit lines during both of the programming and erasing actions is the ground voltage, and 
 wherein the common unselect voltage is one third of a programming voltage required for the programming action for the variable resistance element or an erasing voltage required for the erasing action for the variable resistance element. 
 
     
     
       47. The operating method of the nonvolatile semiconductor memory device according to  claim 18 , wherein
 a voltage applied to one of a selected word line and a selected bit line connected to the selected memory cell among the word lines and the bit lines during both of the programming and erasing actions is the ground voltage, and 
 wherein the common unselect voltage is two thirds of a programming voltage required for the programming action for the variable resistance element or an erasing voltage required for the erasing action for the variable resistance element. 
 
     
     
       48. The operating method of the nonvolatile semiconductor memory device according to  claim 18 , wherein
 a polarity of one of voltages applied to a selected word line and a selected bit line connected to the selected memory cell among the word lines and the bit lines during both of the programming and erasing actions is positive and a polarity of the other thereof is negative, and the absolute values of them is the same, and the unselect voltage is the ground voltage.   
     
     
       49. The operating method of the nonvolatile semiconductor memory device according to  claim 18 , wherein
 the voltage switch circuit applies is further configured to apply the common unselect voltage to a selected word line and selected bit line connected to the selected memory cell, and the unselected word lines and unselected bit lines among the word lines and bit lines in a standby state in which none of the reading, programming, and erasing actions is performed. 
 
     
     
       50. The operating method of the nonvolatile semiconductor memory device according to  claim 18 , wherein
 the material of the variable resistance element is comprises a metal oxide. 
 
     
     
       51. The operating method of the nonvolatile semiconductor memory device according to claim  18  50, wherein
 the metal oxide as the material of the variable resistance element is comprises a transition metal oxide. 
 
     
     
       52. The operating method of the nonvolatile semiconductor memory device according to claim  18  50, wherein
 the metal oxide as the material of the variable resistance element contains comprises Pr and Mn. 
 
     
     
       53. A memory device comprising:
 a memory cell array including memory cells, wherein a first terminal of each memory cell in a same row is connected to a common word line, and wherein a second terminal of each memory cell in a same column is connected to a common bit line; and   a voltage switch circuit configured to apply a voltage for each of a plurality of memory actions to a selected word line and a selected bit line connected to a selected memory cell and to unselected word lines and unselected bit lines according to the plurality of memory actions, wherein the plurality of memory actions include a reading action, a programming action, and an erasing action in the selected memory cell;   wherein the voltage switch circuit is further configured to:
 apply a common unselect voltage to both the unselected word lines and the unselected bit lines during the reading actions; 
 apply the common unselect voltage to both the unselected word lines and the unselected bit lines during the programming action; and 
 apply the common unselect voltage to both the unselected word lines and the unselected bit lines during the erasing action, and wherein the common unselected voltage has an absolute value greater than zero. 
   
     
     
       54. The memory device of claim 53, wherein the voltage switch circuit is further configured to apply the common unselect voltage to at least the unselected word lines and the unselected bit lines during action preparing periods prior to the reading action, the programming action, and the erasing action. 
     
     
       55. The memory device of claim 53, further comprising:
 a memory cell selecting circuit configured to select the selected memory cell from the memory cell array by row or column; and   a reading circuit configured to read information stored in the selected memory cell by detecting an amount of a reading current flowing according to a resistance value of a variable resistance element in the selected memory cell.   
     
     
       56. The memory device of claim 53, wherein the voltage switch circuit is further configured to apply the common unselect voltage to one of the selected word line or the selected bit line and to both of the unselected word line and the unselected bit line and apply a first reading voltage different from the common unselected voltage to the other of the selected word line or the selected bit line during the reading action. 
     
     
       57. The memory device of claim 53, wherein the voltage switch circuit is further configured to apply a first programming voltage higher than the common unselect voltage to one of the selected word line or the selected bit line and apply a second programming voltage lower than the common unselect voltage to the other of the selected word line or the selected bit line during the programming action. 
     
     
       58. The memory device of claim 53, wherein the voltage switch circuit is further configured to apply a first erasing voltage higher than the common unselect voltage to one of the selected word line or the selected bit line and apply a second erasing voltage lower than the common unselect voltage to the other of the selected word line or the selected bit line during the erasing action. 
     
     
       59. The memory device of claim 53, wherein a voltage applied to the selected word line or the selected bit line during both of the programming and erasing actions is the ground voltage, and wherein the common unselect voltage is half or less of a programming voltage for the programming action for the variable resistance element or an erasing voltage for the erasing action for the variable resistance element. 
     
     
       60. The memory device of claim 53, wherein a polarity of a first voltage applied to the selected word line and the selected bit line is positive and a polarity of a second voltage applied to the selected word line and the selected bit line is negative during both of the programming and erasing actions. 
     
     
       61. The memory device of claim 53, wherein the voltage switch circuit is further configured to apply the common unselect voltage to the selected word line, the selected bit line, the unselected word lines, and the unselected bit lines in a standby state in which none of the reading action, the programming action, or the erasing action is performed. 
     
     
       62. A memory device comprising:
 a memory cell array including memory cells, wherein a first terminal of each memory cell in a same row is connected to a common word line, and wherein a second terminal of each memory cell in a same column is connected to a common bit line; and   a voltage switch circuit configured to apply a voltage for each of a plurality of memory actions to a selected word line and a selected bit line connected to a selected memory cell and to un-selected word lines and unselected bit lines according to the plurality of memory actions, wherein the plurality of memory actions include a reading action and a programming action in the selected memory cell;   wherein the voltage switch circuit is further configured to:
 apply a common unselect voltage to the unselected word lines during the reading actions and the programming actions and apply the common unselect voltage to the unselected bit lines during the reading actions and the erasing actions; or 
 apply the common unselect voltage to the unselected bit lines during the reading actions and the programming actions and apply the common unselect voltage to the unselected word lines during the reading actions and the erasing actions, wherein the common unselect voltage has an absolute value greater than zero. 
   
     
     
       63. The memory device of claim 62, wherein the memory cells comprise a variable resistance element having a resistance value configured to reversibly change in response to electric pulse application. 
     
     
       64. The memory device of claim 63, further comprising:
 a memory cell selecting circuit configured to select the selected memory cell from the memory cell array by row or column; and   a reading circuit configured to read information stored in the selected memory cell by detecting an amount of a reading current flowing according to a resistance value of the variable resistance element in the selected memory cell.   
     
     
       65. The memory device of claim 63, wherein the variable resistance element comprises resistance random access memory, and wherein the voltage switch circuit is further configured to apply the common unselect voltage to the other of the unselected word lines and the unselected bit lines at least during the both the reading action and the erasing action. 
     
     
       66. The memory device of claim 62, wherein the plurality of memory actions further include an erasing action. 
     
     
       67. A memory device comprising:
 a memory cell array including memory cells, wherein a first terminal of each memory cell in a same row is connected to a common word line, and wherein a second terminal of each memory cell in a same column is connected to a common bit line; and   a voltage switch circuit configured to apply a voltage for each of a plurality of memory actions to a selected word line and a selected bit line connected to a selected memory cell and to unselected word lines and unselected bit lines according to the plurality of memory actions, wherein the plurality of memory actions include a reading action and a programming action in the selected memory cell;   wherein the voltage switch circuit is further configured to:
 apply a common unselect voltage to both the unselected word lines and the unselected bit lines during the reading actions; and 
 apply the common unselect voltage to both the unselected word lines and the unselected bit lines during the programming action, and wherein the unselected voltage has an absolute value greater than zero. 
   
     
     
       68. The nonvolatile semiconductor memory device according to claim 1, wherein the common unselect voltage is the same during each of the reading, programming, and erasing actions.