Semiconductor device and method of fabricating the same

Abstract

An adhesion layer made from Al film or Ti film is formed on Cu electrode pad portions as external connection terminals of a Cu interconnection layer of an LSI formed on the surface layer of a semiconductor substrate. A BLM film having a stacked structure of Cr/Cu/Au or Ti/Cu/Au is formed on the adhesion layer. Solder ball bumps made from Pb and Sn are formed on the BLM film. The adhesion layer ensures a high adhesion strength and a high electric contact characteristic between the Cu electrode pad portions and the BLM film, that is, between the Cu electrode pads and the solder ball bumps.

What is claimed is: 
     
       1. A semiconductor device comprising:
 A semiconductor substrate in contact with a multilayer interconnection layer, said multilayer interconnection layer comprising an electrode pad portion as an external connection terminal of the multilayer interconnection layer, said multilayer interconnection layer and said electrode pad portion made from copper or an alloy containing copper;   an adhesion layer formed directly on the electrode pad portion such that the adhesion layer is in contact with the electrode pad portion;   a barrier layer formed on the adhesion layer, wherein such barrier layer has a stacked structure of at least two different types of metal; and   a solder bump formed on the barrier layer.   
     
     
       2. A semiconductor device according to  claim 1 , wherein said adhesion layer is made from at least one kind of metal selected from a group consisting of Al, Cr, Co, Ni, Mo, Ag, Ta, W and Au, or an alloy containing said at least one kind of metal. 
     
     
       3. A semiconductor device comprising:
 a semiconductor substrate in contact with a multilayer interconnection layer, said multilayer interconnection layer comprising an electrode pad portion as an external connection terminal of the multilayer interconnection layer, said multilayer interconnection layer and said electrode pad portion made from copper or an alloy containing copper;   an adhesion layer formed directly on the electrode pad portion such that the adhesion layer is in contact with the electrode pad portion;   a first passivation layer formed on said adhesion layer;   a barrier layer formed on the adhesion layer, wherein such barrier layer has a stacked structure of at least two different types of metal; and   a solder bump formed on the barrier layer,   wherein said adhesion layer has an upper surface including a first portion that is in contact with said first passivation layer and a second portion that contacts a bottom surface of said barrier layer.    
     
     
       4. A semiconductor device according to claim 3 wherein said first passivation layer has a lower surface that is in contact with said adhesion layer, an upper surface that is in contact with said barrier layer, and a side surface that is in contact with said barrier layer, wherein said side surface extends from said lower surface to said upper surface.  
     
     
       5. A semiconductor device according to claim 3, wherein said adhesion layer comprises Al.  
     
     
       6. A semiconductor device according to claim 3, wherein said adhesion layer comprises Co.  
     
     
       7. A semiconductor device according to claim 3, wherein said adhesion layer comprises Ni.  
     
     
       8. A semiconductor device according to claim 3, wherein said adhesion layer comprises Ta.  
     
     
       9. A semiconductor device according to claim 3, wherein said adhesion layer comprises W.  
     
     
       10. A semiconductor device according to claim 3, wherein said adhesion layer comprises Au.  
     
     
       11. A semiconductor device according to claim 3, further comprising a second passivation layer formed between said electrode pad portion and said first passivation layer.  
     
     
       12. A semiconductor device according to claim 11, wherein said second passivation layer has a lower surface that is in contact with said electrode pad portion, an upper surface that is in contact with said first passivation layer, and a side surface that is in contact with said first passivation layer, wherein said side surface extends from said lower surface to said upper surface.  
     
     
       13. A semiconductor device according to claim 11, wherein said first passivation layer is made of polyimide, and said second passivation layer is made of silicon nitride.  
     
     
       14. A semiconductor device according to claim 3, wherein a thickness of the barrier layer is thicker than a thickness of the adhesion layer.  
     
     
       15. A semiconductor device according to claim 3, wherein the multilayer interconnection layer and the electrode pad portion are made from the same material.  
     
     
       16. A semiconductor device according to claim 3, wherein said adhesion layer substantially contacts an entire bottom surface of said barrier layer.  
     
     
       17. A semiconductor device comprising:
 a semiconductor substrate in contact with a multilayer interconnection layer, said multilayer interconnection layer comprising an electrode pad portion as an external connection terminal of the multilayer interconnection layer, said multilayer interconnection layer and said electrode pad portion made from copper or an alloy containing copper;   an adhesion layer formed directly on the electrode pad portion such that the adhesion layer is in contact with said electrode pad portion;   a first passivation layer formed on said adhesion layer,   a barrier layer formed on said adhesion layer, wherein such barrier layer has a stacked structure of at least two different types of metal; and   a solder bump formed on the barrier layer,   wherein said first passivation layer has an opening through which said barrier layer is electrically connected to said adhesion layer.    
     
     
       18. A semiconductor device according to claim 17, wherein said first passivation layer is formed directly on said adhesion layer, and said barrier layer is formed directly on said adhesion layer.  
     
     
       19. A semiconductor device according to claim 17, wherein said adhesion layer comprises Ta.  
     
     
       20. A semiconductor device according to claim 17, wherein a thickness of the barrier layer is thicker than a thickness of the adhesion layer.  
     
     
       21. A semiconductor device according to claim 17, wherein the multilayer interconnection layer and the electrode pad portion are made from the same material.  
     
     
       22. A semiconductor device according to claim 17, wherein said adhesion layer substantially contacts an entire bottom surface of said barrier layer.  
     
     
       23. A semiconductor device according to claim 17, further comprising a second passivation layer formed between said electrode pad portion and said first passivation layer.  
     
     
       24. A semiconductor device according to claim 23, wherein said second passivation layer has a lower surface that is in contact with said electrode pad portion, an upper surface that is in contact with said first passivation layer, and a side surface that is in contact with said first passivation layer, wherein said side surface extends from said lower surface to said upper surface.