Method and controller for performing a sequence of commands

Abstract

The embodiments described herein provide a method and controller for performing a sequence of commands. In one embodiment, a controller receives a command from a host to perform a memory operation in a flash memory device, wherein the command comprises at least one bit that indicates whether the command is a stand-alone command or is part of a sequence of commands. The controller analyzes the at least one bit to determine whether the at least one bit indicates that the command is a stand-alone command or is part of a sequence of commands. If the at least one bit indicates that the command is a stand-alone command, the controller performs the command. If the at least one bit indicates that the command is part of a sequence of commands, the controller performs the command as part of the sequence of commands.

What is claimed is: 
     
       1. A method for performing a sequence of commands, the method comprising:
 performing in a controller in communication with a host and a flash memory device:
 receiving a command from the host to perform a memory operation in the flash memory device, wherein the command comprises at least one bit that indicates whether the command is a stand-alone command or is part of a sequence of commands; 
 analyzing the at least one bit to determine whether the at least one bit indicates that the command is a standalone command or is part of a sequence of commands; 
 if the at least one bit indicates that the command is a stand-alone command, performing the command; and 
 if the at least one bit indicates that the command is part of a sequence of commands, performing the command as part of the sequence of commands, wherein each of the commands in the sequence of commands includes a command code. 
   
     
     
       2. The method of claim  1  3, wherein the flash memory device is organized into a plurality of planes, and wherein each command in the sequence of commands is performed in a different one of the plurality of planes. 
     
     
       3. The method of  claim 1 , A method for performing a sequence of commands, the method comprising:
 performing in a controller in communication with a host and a flash memory device:
 receiving a command from the host to perform a memory operation in the flash memory device, wherein the command comprises at least one bit that indicates whether the command is a stand-alone command or is part of a sequence of commands; 
 analyzing the at least one bit to determine whether the at least one bit indicates that the command is a stand-alone command or is part of a sequence of commands; 
 if the at least one bit indicates that the command is a stand-alone command, performing the command; and 
 if the at least one bit indicates that the command is part of a sequence of commands, performing the command as part of the sequence of commands, wherein each of the commands in the sequence of commands includes a command code wherein the sequence of commands comprises an atomic command sequence, and wherein the commands in the sequence of commands are performed together as a group. 
 
 
     
     
       4. The method of claim  1  3, wherein the sequence of commands comprise sequential commands with incremental addresses. 
     
     
       5. The method of  claim 1 , A method for performing a sequence of commands, the method comprising:
 performing in a controller in communication with a host and a flash memory device:
 receiving a command from the host to perform a memory operation in the flash memory device, wherein the command comprises at least one bit that indicates whether the command is a stand-alone command or is part of a sequence of commands; 
 analyzing the at least one bit to determine whether the at least one bit indicates that the command is a stand-alone command or is part of a sequence of commands; 
 if the at least one bit indicates that the command is a stand-alone command, performing the command; and 
 if the at least one bit indicates that the command is part of a sequence of commands, performing the command as part of the sequence of commands, wherein each of the commands in the sequence of commands includes a command code;  
 
 wherein the at least one bit is a single bit and wherein the single bit is one of a plurality of reserved address bits. 
 
     
     
       6. The method of  claim 5 , wherein the single bit is one of a plurality of reserved address bits. 
     
     
       7. The method of claim  1  3, wherein at least one bit in a last command in the sequence of commands indicates that the command is a stand-alone command. 
     
     
       8. The method of claim  1  3, wherein the sequence of commands are received by the controller one command at a time. 
     
     
       9. The method of  claim 8  further comprising sending a response back to the host either after the entire sequence of commands have been received or after each command in the sequence of commands has been received. 
     
     
       10. A controller for performing a sequence of commands, the controller comprising:
 a first interface configured to transfer data between a host and the controller;   a second interface configured to transfer data between the controller and a flash memory device; and   circuitry operative to:
 receive a command from the host to perform a memory operation in the flash memory device, wherein the command comprises at least one bit that indicates whether the command is a stand-alone command or is part of a sequence of commands; 
 analyze the at least one bit to determine whether the at least one bit indicates that the command is a stand-alone command or is part of a sequence of commands; 
 if the at least one bit indicates that the command is a stand-alone command, perform the command; and 
 if the at least one bit indicates that the command is part of a sequence of commands, perform the command as part of the sequence of commands, wherein each of the commands in the sequence of commands includes a command code. 
   
     
     
       11. The controller of claim  10  12, wherein the flash memory device is organized into a plurality of planes, and wherein each command in the sequence of commands is performed in a different one of the plurality of planes. 
     
     
       12. The controller of  claim 10 , A controller for performing a sequence of commands, the controller comprising:
 a first interface configured to transfer data between a host and the controller; 
 a second interface configured to transfer data between the controller and a flash memory device; and 
 circuitry operative to:
 receive a command from the host to perform a memory operation in the flash memory device, wherein the command comprises at least one bit that indicates whether the command is a stand-alone command or is part of a sequence of commands; 
 analyze the at least one bit to determine whether the at least one bit indicates that the command is a stand-alone command or is part of a sequence of commands; 
 if the at least one bit indicates that the command is a stand-alone command, perform the command; and 
 if the at least one bit indicates that the command is part of a sequence of commands, perform the command as part of the sequence of commands, wherein each of the commands in the sequence of commands includes a command code;  
 
 wherein the sequence of commands comprises an atomic command sequence, and wherein the commands in the sequence of commands are performed together as a group. 
 
     
     
       13. The controller of claim  10  12, wherein the sequence of commands comprise sequential commands with incremental addresses. 
     
     
       14. The controller of  claim 10 , wherein the at least one bit is a single bit. 
     
     
       15. The controller of  claim 14 , A controller for performing a sequence of commands, the controller comprising:
 a first interface configured to transfer data between a host and the controller; 
 a second interface configured to transfer data between the controller and a flash memory device; and 
 circuitry operative to:
 receive a command from the host to perform a memory operation in the flash memory device, wherein the command comprises at least one bit that indicates whether the command is a stand-alone command or is part of a sequence of commands; 
 analyze the at least one bit to determine whether the at least one bit indicates that the command is a stand-alone command or is part of a sequence of commands; 
 if the at least one bit indicates that the command is a stand-alone command, perform the command; and 
 if the at least one bit indicates that the command is part of a sequence of commands, perform the command as part of the sequence of commands, wherein each of the commands in the sequence of commands includes a command code; 
 
 wherein the at least one bit is a single bit, and  
 wherein the single bit is one of a plurality of reserved address bits. 
 
     
     
       16. The controller of claim  10  12, wherein at least one bit in a last command in the sequence of commands indicates that the command is a stand-alone command. 
     
     
       17. The controller of claim  10  12, wherein the sequence of commands are received by the controller one command at a time. 
     
     
       18. The controller of  claim 17 , wherein the processor is further operative to send a response back to the host either after the entire sequence of commands have been received or after each command in the sequence of commands has been received. 
     
     
       19. The controller of claim  10  12, wherein at least one of the first and second interfaces comprises a NAND interface configured to transfer data using a NAND interface protocol. 
     
     
       20. The controller of claim  10  12, wherein both the first and second interfaces comprise a NAND interface configured to transfer data using a NAND interface protocol. 
     
     
       21. The method of claim 3, wherein the flash memory device comprises a three-dimensional memory.  
     
     
       22. The method of claim 21, wherein the three-dimensional memory is a passive element array.  
     
     
       23. The method of claim 21, wherein word lines and/or bit lines in the three-dimensional memory are shared between levels.  
     
     
       24. The controller of claim 12, wherein the flash memory device comprises a three-dimensional memory.  
     
     
       25. The controller of claim 24, wherein the three-dimensional memory is a passive element array.  
     
     
       26. The controller of claim 24, wherein word lines and/or bit lines in the three-dimensional memory are shared between levels.  
     
     
       27. The method of claim 5, wherein the flash memory device comprises a three-dimensional memory.  
     
     
       28. The method of claim 27, wherein the three-dimensional memory is a passive element array.  
     
     
       29. The method of claim 27, wherein word lines and/or bit lines in the three-dimensional memory are shared between levels.  
     
     
       30. The controller of claim 15, wherein the flash memory device comprises a three-dimensional memory.  
     
     
       31. The controller of claim 30, wherein the three-dimensional memory is a passive element array.  
     
     
       32. The controller of claim 30, wherein word lines and/or bit lines in the three-dimensional memory are shared between levels.