High-speed CMOS image sensor

Abstract

A CMOS image sensor having two ASPs can reduce increasing design difficulty as arising from a pixel array becoming larger and larger. The image sensor includes a selection circuit for transmitting outputs of CDS circuits through four divided buses to reduce parasitic loading and achieve high-speed operation. Then, the selecting circuit transmits red and blue pixels to a first ASP, and transmits green pixels to a second ASP, so as to relax the specification requirements of the ASP.

What is claimed is: 
     
       1. A complementary metal oxide semiconductor (CMOS) image sensor for high-speed operation comprising:
 a pixel array comprising a plurality of first pixels, a plurality of second pixels, and a plurality of third pixels;   a plurality of correlation double sampling (CDS) circuits coupled to corresponding columns of the pixel array; and   a selection circuit comprising:
 a plurality of input ends coupled to each CDS circuit of the plurality of CDS circuits respectively; 
 a first output end; 
 a second output end; 
 a first switch coupling a 4n−3th CDS circuit to a first analog signal processor (ASP); 
 a second switch coupling the 4n−3th CDS circuit to a second ASP; 
 a third switch coupling a 4n−2th CDS circuit to the first ASP; 
 a fourth switch coupling the 4n−2th CDS circuit to the second ASP; 
 a fifth switch coupling a 4n−1th CDS circuit to the first ASP; 
 a sixth switch coupling the 4n−1th CDS circuit to the second ASP; 
 a seventh switch coupling a 4nth CDS circuit to the first ASP; and 
 a eighth switch coupling the 4nth CDS circuit and to the second ASP; 
 wherein n is a positive integer; 
   wherein the first ASP is coupled to the first output end of the selection circuit for processing data of the plurality of first pixels and the plurality of second pixels;   wherein the second ASP is coupled to the second output end of the selection circuit for processing data of the plurality of third pixels.   
     
     
       2. The CMOS image sensor of  claim 1 , wherein the plurality of CDS circuits are coupled to a same side of each column of the pixel array respectively. 
     
     
       3. The CMOS image sensor of  claim 1 , wherein the plurality of first pixels, the plurality of second pixels, and the plurality of third pixels are red pixel pixels, blue pixels, and green pixels respectively. 
     
     
       4. A complementary metal oxide semiconductor (CMOS) image sensor for high-speed operation comprising:
 a pixel array comprising a plurality of first pixels, a plurality of second pixels, and a plurality of third pixels; 
 a plurality of correlation double sampling (CDS) circuits; 
 an output circuit comprising a plurality of input ends coupled to each CDS circuit respectively, a first output end, and a second output end; 
 an auxiliary CDS circuit; 
 a switch circuit comprising:
 a first group of switches coupling an nth column of the pixel array to the nth CDS circuit; and 
 a second group of switches coupling the first column of the pixel array to the auxiliary CDS circuit, and coupling an n+ 1 th) (n+1)th column of the pixel array to the nth CDS circuit; 
 
 a first analog signal processor (ASP) coupled to the first output end of the output circuit for processing data of the plurality of first pixels and the plurality of second pixels; and 
 a second analog signal processor (ASP) coupled to the second output end of the output circuit for processing data of the plurality of third pixels; 
 wherein the auxiliary CDS circuit is coupled between the switch circuit and the output circuit; wherein a  2 n− 1 th (2n−1)th CDS circuit is coupled to the first ASP via the output circuit, the auxiliary CDS circuit and a 2nth CDS circuit are coupled to the second ASP via the output circuit, and n is a positive integer. 
 
     
     
       5. The CMOS image sensor of  claim 4 , wherein the plurality of CDS circuits are coupled to a same side of each column of the pixel array respectively. 
     
     
       6. The CMOS image sensor of  claim 4 , wherein the plurality of first pixels, the plurality of second pixels, and the plurality of third pixels are red pixels, blue pixels, and green pixels respectively. 
     
     
       7. A complementary metal oxide semiconductor (CMOS) image sensor for high-speed operation comprising:
 a pixel array comprising a plurality of first pixels, a plurality of second pixels, and a plurality of third pixels; 
 a plurality of correlation double sampling (CDS) circuits; 
 an output circuit comprising a plurality of input ends coupled to each CDS circuit respectively, a first output end, and a second output end; 
 a switch circuit comprising:
 a first group of switches coupling a mth column of the pixel array to the mth CDS circuit; and 
 a second group of switches coupling a  2 n− 1  ( 2 n− 1 )th column of the pixel array to a  2 nth CDS circuit, and coupling the 2nth column of the pixel array to the  2 n− 1 th (2n−1)th CDS circuit; 
 wherein m and n are positive integers, 
 
 a first analog signal processor (ASP) coupled to the first output end of the output circuit for processing data of die the first pixels and the second pixels; and 
 a second analog signal processor (ASP) coupled to the second output end of the output circuit for processing data of the third pixels; 
 wherein the 2nth CDS is coupled to the first ASP via the output circuit, the  2 n− 1 th (2n−1)th CDS circuit is coupled to the second ASP via the output circuit. 
 
     
     
       8. A complementary metal oxide semiconductor (CMOS) image sensor for high-speed operation comprising:
 a pixel array comprising a plurality of first pixels, a plurality of second pixels, and a plurality of third pixels; 
 a plurality of correlation double sampling (CDS) circuits, wherein the plurality of CDS circuits comprises a first group of CDS circuits coupled to a first analog signal processor (ASP) which processes data of the first pixels and the second pixels, and a second group of CDS circuits coupled to a second ASP which processes data of the third pixels; 
 a switch circuit comprising:
 a first group of switches coupling a  2 n− 1 th (2n−1)th column of the pixel array to the n+ 1 th (n+1)th CDS circuit of the first group of CDS circuit circuits and coupling the 2nth column of the pixel array to the n+ 1 th (n+1)th CDS circuit of the second group of CDS circuit circuits; and 
 a second group of switches coupling a 2nth column of the pixel array to the nth CDS circuit of the first group of CDS circuit circuits and coupling the  2 n− 1 th (2n−1)th column of the pixel array to the nth CDS circuit of the second group of CDS circuit circuits; 
 
 wherein n is a positive integer. 
 
     
     
       9. The CMOS image sensor of claim 7, wherein the plurality of CDS circuits are on the same side of the pixel array. 
     
     
       10. The CMOS image sensor of claim 9, wherein the plurality of CDS circuits are arranged as a single row.  
     
     
       11. The CMOS image sensor of claim 8, wherein the plurality of CDS circuits are on the same side of the pixel array.  
     
     
       12. The CMOS image sensor of claim 11, wherein the first group of CDS circuits are arranged as a first row, and the second group of CDS circuits are arranged as a second row.  
     
     
       13. The CMOS image sensor of claim 12, further including at least one divided data bus coupled between the plurality of CDS circuits and the first and second ASPs. 
     
     
       14. A complementary metal oxide semiconductor (CMOS) image sensor for high-speed operation comprising:
 a pixel array comprising a plurality of first pixels, a plurality of second pixels, and a plurality of third pixels;   a plurality of correlation double sampling (CDS) circuits, wherein the plurality of CDS circuits comprises a first group of CDS circuits coupled to a first analog signal processor (ASP) which processes data of the first pixels and the second pixels, and a second group of CDS circuits coupled to a second ASP which processes data of the third pixels;   a switch circuit comprising:
 a first group of switches coupling (n+1)th column of the pixel array to the nth CDS circuit of the first group of CDS circuits and coupling the nth column of the pixel array to the nth CDS circuit of the second group of CDS circuits; and 
 a second group of switches coupling a nth column of the pixel array to the nth CDS circuit of the first group of CDS circuits and coupling the (n+1)th column of the pixel array to the nth CDS circuit of the second group of CDS circuits; 
   wherein n is a positive integer and the plurality of CDS circuits are on the same side of the pixel array.   
     
     
       15. The CMOS image sensor of claim 14, wherein the first group of CDS circuits are arranged as a first row, and the second group of CDS circuits are arranged as a second row.  
     
     
       16. The CMOS image sensor of claim 15, further including at least one divided data bus coupled between the plurality of CDS circuits and the first and second ASPs. 
     
     
       17. A complementary metal oxide semiconductor (CMOS) image sensor for high-speed operation comprising:
 a pixel array comprising a plurality of first pixels, a plurality of second pixels, and a plurality of third pixels;   a plurality of correlation double sampling (CDS) circuits;   a switch circuit arranged on a side of the pixel array, comprising:
 a first group of switches coupling a mth column of the pixel array to the mth CDS circuit; and 
 a second group of switches coupling a (2n−1)th column of the pixel array to a 2nth CDS circuit, and coupling the 2nth column of the pixel array to the (2n−1)th CDS circuit; 
 wherein m and n are positive integers, 
   wherein the 2nth CDS is coupled to a first ASP which processes data of the first pixels and the second pixels, the (2n−1)th CDS circuit is coupled to a second ASP which processes data of the third pixels.   
     
     
       18. The CMOS image sensor of claim 17, wherein the plurality of CDS circuits are on the side of the pixel array. 
     
     
       19. The CMOS image sensor of claim 18, wherein the plurality of CDS circuits are arranged as a single row. 
     
     
       20. A complementary metal oxide semiconductor (CMOS) image sensor for high-speed operation comprising:
 a pixel array comprising a plurality of first pixels, a plurality of second pixels, and a plurality of third pixels;   a plurality of correlation double sampling (CDS) circuits, wherein the plurality of CDS circuits comprises a first group of CDS circuits coupled to a first analog signal processor (ASP) which processes data of the first pixels and the second pixels, and a second group of CDS circuits coupled to a second ASP which processes data of the third pixels;   a switch circuit, coupled between the pixel array and the plurality of CDS circuits comprising:
 a first group of switches coupling a first set of columns of the pixel array to a first set of CDS circuits of the first group of CDS circuits and coupling a second set of columns of the pixel array to a first set of CDS circuits of the second group of CDS circuits; and 
 a second group of switches coupling a third set of columns of the pixel array to a second set of CDS circuits of the first group of CDS circuits and coupling a fourth set of columns of the pixel array to a second set of CDS circuits of the second group of CDS circuits; 
 wherein the switch circuit and the plurality of CDS circuits are on a same single side of the pixel array. 
   
     
     
       21. The CMOS image sensor of claim 20, wherein the first and second sets of columns of the pixel array are the fourth and third sets of columns of the pixel array, respectively. 
     
     
       22. The CMOS image sensor of claim 20, wherein the plurality of CDS circuits are arranged as a single row. 
     
     
       23. The CMOS image sensor of claim 20, wherein the first group of CDS circuits are arranged as a first row, and the second group of CDS circuits are arranged as a second row. 
     
     
       24. The CMOS image sensor of claim 20, further including at least one divided data bus coupled between the plurality of CDS circuits and the first and second ASPs. 
     
     
       25. A complementary metal oxide semiconductor (CMOS) image sensor for high-speed operation comprising:
 a pixel array comprising a plurality of first pixels, a plurality of second pixels, and a plurality of third pixels;   a plurality of correlation double sampling (CDS) circuits;   a switch circuit arranged on a single side of the pixel array, comprising:
 a first group of switches coupling a first set of columns of the pixel array to a first group of CDS circuits of the plurality of CDS circuits; and 
 a second group of switches coupling a second set of columns of the pixel array to a second group of CDS circuits of the plurality of CDS circuits, and coupling a third set of columns of the pixel array to a third group of CDS circuits of the plurality of CDS circuits; 
   wherein the first group of CDS circuits are coupled to a first ASP which processes data of the first pixels and the second pixels, and the second group of CDS circuits are coupled to a second ASP which processes data of the third pixels, and   wherein the switch circuit and the plurality of CDS circuits are on a same single side of the pixel array.   
     
     
       26. The CMOS image sensor of claim 25, wherein the first set of columns of the pixel array include the second and third sets of columns of the pixel array, and the first group of CDS circuits of the plurality of CDS circuits include the second and third groups of CDS circuits of the plurality of CDS circuits. 
     
     
       27. The CMOS image sensor of claim 25, wherein the plurality of CDS circuits are arranged as a single row. 
     
     
       28. The CMOS image sensor of claim 25, wherein the first group of CDS circuits are arranged as a first row, and the second group of CDS circuits are arranged as a second row. 
     
     
       29. The CMOS image sensor of claim 25, further including at least one divided data bus coupled between the plurality of CDS circuits and the first and second ASPs. 
     
     
       30. A complementary metal oxide semiconductor (CMOS) image sensor for high-speed operation comprising:
 a pixel array comprising a plurality of first pixels, a plurality of second pixels, and a plurality of third pixels;   a plurality of correlation double sampling (CDS) circuits coupled to corresponding columns of the pixel array; and   a selection circuit comprising:
 a plurality of input ends coupled to each CDS circuit of the plurality of CDS circuits respectively; 
 a first output end; 
 a second output end; 
 a plurality of switches, comprising a first group of switches coupling a first group of CDS circuits of the plurality of CDS circuits to a first analog signal processor (ASP), and a second group of switches coupling a second group CDS circuits of the plurality of CDS circuits to a second ASP; 
   wherein the first ASP is coupled to the first output end of the selection circuit for processing data of the plurality of first pixels and the plurality of second pixels; wherein the second ASP is coupled to the second output end of the selection circuit for processing data of the plurality of third pixels, and   wherein the plurality of switches and the plurality of CDS circuits are on a same single side of the pixel array.   
     
     
       31. The CMOS image sensor of claim 30, wherein the plurality of CDS circuits are arranged as a single row. 
     
     
       32. The CMOS image sensor of claim 30, wherein the selection circuit further includes at least one divided data bus coupled between the plurality of CDS circuits and the plurality of switches. 
     
     
       33. The CMOS image sensor of claim 4, wherein the output circuit includes at least one divided data bus. 
     
     
       34. A complementary metal oxide semiconductor (CMOS) image sensor for high-speed operation comprising:
 a pixel array comprising a plurality of pixels;   a plurality of correlation double sampling (CDS) circuits coupled to corresponding columns of the pixel array; and   a selection circuit comprising:
 a plurality of input ends coupled to each CDS circuit of the plurality of CDS circuits respectively; 
 a first output end coupled to a first analog signal processor (ASP); 
 a second output end coupled to a second analog signal processor (ASP); and 
 a plurality of switches, comprising a plurality of switches each coupling between multiple CDS circuits of the plurality of CDS circuits and one of the first output end and the second output end. 
   
     
     
       35. The CMOS image sensor of claim 34, wherein the plurality of switches and the plurality of CDS circuits are on a same single side of the pixel array. 
     
     
       36. The CMOS image sensor of claim 34, wherein the plurality of CDS circuits are arranged as a single row. 
     
     
       37. The CMOS image sensor of claim 34, wherein the selection circuit further includes at least one divided data bus coupled between the plurality of CDS circuits and the plurality of switches.