Duty detection circuit, clock generation circuit including the duty detection circuit, and semiconductor device

Abstract

To provide a duty detection circuit including: a plurality of duty detectors that detect a duty ratio of internal clocks; a controller that controls the plurality of duty detectors so that the plurality of duty detectors operates in different phases from one another; and an output selecting unit that selects one of duty detection signals from the plurality of duty detectors. According to the present invention, since the duty detectors operate in the different phases from one another, the output selecting unit can output a duty detection signal with a higher frequency than a generation frequency with which each duty detector generates the duty detection signal. Accordingly, when the duty detection circuit according to the present invention is used to adjust a clock of the DLL circuit, a control period of the DLL circuit can be reduced.

What is claimed is: 
     
       1. A semiconductor device comprising:
 a plurality of duty detectors that detect duty ratios of an internal clock to generate duty detection signals, respectively; 
 a control circuit that controls the duty detectors so that the duty detectors operate in different phases from one another; and 
 an output selecting unit that selects one of the duty detection signals, wherein the output selecting unit receives from the control circuit a plurality of selection signals, each of the plurality of selection signals corresponding to a respective one of the duty detection signals, and wherein the selection of one of the duty detection signals is dependent on a selection signal corresponding to the selected duty detection signal being activated. 
 
     
     
       2. The semiconductor device as claimed in  claim 1 , A semiconductor device comprising:
 a plurality of duty detectors that detect duty ratios of an internal clock to generate duty detection signals, respectively; 
 a control circuit that controls the duty detectors so that the duty detectors operate in different phases from one another; and 
 an output selecting unit that selects one of the duty detection signals;  
 wherein each of the duty detectors takes n cycles of the internal clock since starting a duty detection operation until the output selecting unit outputs an associated duty detection signal, where n is an integer equal to or greater than 2, 
 the number of the duty detectors is m, where m is an integer equal to or greater than 2, and 
 the m is a divisor of the n. 
 
     
     
       3. The semiconductor device as claimed in  claim 2 , wherein the control circuit controls the duty detectors so that different duty detectors start duty detection operations at intervals of n/m cycles of the internal clock. 
     
     
       4. The semiconductor device as claimed in  claim 2 , wherein the output selecting unit selects different duty detection signals out of the duty detection signals at intervals of n/m cycles of the internal clock. 
     
     
       5. The semiconductor device as claimed in  claim 1 , wherein the output selecting unit includes:
 a selector that passes one of the duty detection signals; and 
 a latch circuit that latches the duty detection signal having passed through the selector. 
 
     
     
       6. The semiconductor device as claimed in  claim 1 , A semiconductor device comprising:
 a plurality of duty detectors that detect duty ratios of an internal clock to generate duty detection signals, respectively; 
 a control circuit that controls the duty detectors so that the duty detectors operate in different phases from one another; and 
 an output selecting unit that selects one of the duty detection signals;  
 wherein each of the duty detectors includes: 
 an integral capacitor charged or discharged in response to the internal clock; and 
 an amplifier circuit that amplifies a potential difference between a charging voltage of the integral capacitor and a reference voltage to generate the duty detection signal. 
 
     
     
       7. The semiconductor device as claimed in  claim 1 , further comprising: A semiconductor device comprising:
 a plurality of duty detectors that detect duty ratios of an internal clock to generate duty detection signals, respectively; 
 a control circuit that controls the duty detectors so that the duty detectors operate in different phases from one another; 
 an output selecting unit that selects one of the duty detection signals;  
 a DLL circuit that controls a phase of the internal clock; and 
 first and second replica buffers, wherein 
 the internal clock includes first and second internal clocks different in phase, and the DLL circuit includes: 
 a first delay line that generates a third internal clock by delaying a first external clock; 
 a second delay line that generates a fourth internal clock by delaying a second external clock; 
 a first phase comparison circuit that determines a phase difference between the first external clock and the first internal clock; 
 a first delay control circuit that controls a delay amount of the first delay line based on a determination result of the first phase comparison circuit; and 
 a second delay control circuit that controls a delay amount of the second delay line based on the duty detection signal, and wherein 
 the first replica buffer generates the first internal clock in response to the third internal clock, and 
 the second replica buffer generates the second internal clock in response to the fourth internal clock. 
 
     
     
       8. The semiconductor device as claimed in  claim 7 , wherein
 the DLL circuit further includes a second phase comparison circuit that determines a phase difference between the second external clock and the second internal clock, and 
 the second delay control circuit includes: 
 a first mode of controlling the delay amount of the second delay line based on a determination result of the second phase comparison circuit; and 
 a second mode of controlling the delay amount of the second delay line based on the duty detection signal. 
 
     
     
       9. The semiconductor device as claimed in  claim 7 , further comprising a clock control circuit that generates an operation clock for the duty detection circuit and the DLL circuit, wherein
 the clock control circuit sets a frequency of the operation clock relatively high when the DLL circuit is in an unlocked state, and sets the frequency of the operation clock relatively low when the DLL circuit is in a locked state. 
 
     
     
       10. The semiconductor device as claimed in  claim 9 , wherein the first delay control circuit loads a determination result of the first phase comparison circuit a plurality of times in response to the operation clock, and controls the delay amount of the first delay line based on a plurality of the determination results. 
     
     
       11. The semiconductor device as claimed in  claim 9 , wherein the second delay control circuit loads the duty detection signal a plurality of times in response to the operation clock, and controls the delay amount of the second delay line based on a plurality of the duty detection signals. 
     
     
       12. The semiconductor device as claimed in  claim 7 , further comprising:
 an internal circuit that generates output data; and 
 an output buffer that outputs the output data to outside in response to the third and fourth internal clocks, wherein 
 the first and second replica buffers each have an impedance substantially equal to an impedance of the output buffer. 
 
     
     
       13. A device comprising:
 a first terminal receiving an external clock signal; 
 a clock generating circuit coupled to the first terminal, including first and second circuit units, the first circuit unit generating an internal clock signal in response to the external clock signal, the second circuit unit including a plurality of detection portions detecting a plurality of duty ratios of the internal clock signal respectively during a plurality of first time periods different in timing starting and terminating from each other and output a plurality of duty detection signals, and the first circuit unit receiving one of the duty detection signals and adjusting a duty ratio of the internal clock signal in response to the one of the duty detection signals. 
 
     
     
       14. The device as claimed in  claim 13 , wherein the detection potions of the second circuit unit output the detection signals at timings different from each other. 
     
     
       15. The device as clamed in  claim 13 , wherein one of the first time periods overlaps partly with another one of the first time periods. 
     
     
       16. The device as claimed in  claim 13 , wherein the first time periods are equal in length of time to each other. 
     
     
       17. The device as claimed in  claim 13 , wherein the clock generating circuit includes a control circuit supplying the detection portions correspondingly with a plurality of first control signals in response to the external clock signal, the first control signals being activated at timings different from each other and deactivated at timings different from each other, and each of the detection portions starts detecting corresponding one of the duty ratios in response to an activation of corresponding one of the first control signals and terminates detecting the corresponding one of the duty ratios in response to an inactivation of the corresponding one of the first control signals. 
     
     
       18. The device as claimed in  claim 13 , wherein each of the detection portions detects a second time period in which the internal clock signal takes a first logic level during a corresponding one of the first time periods, detects a third time period in which the internal clock signal takes a second logic level different from the first logic level during the corresponding one of the first time periods, and compares the second time period and the third time period so as to generate one of the duty detection signals. 
     
     
       19. The device as claimed in  claim 13 , wherein each of the detection portions includes a first capacitor discharged during a second time period in which the internal clock signal takes a first logic level, a second capacitor discharged during a third time period in which the internal clock signal takes a second logic level different from the first logic level, and an amplifier circuit amplifying a potential difference between the first capacitor and the second capacitor so as to generate a corresponding one of the duty detection signals. 
     
     
       20. The device as claimed in  claim 13 , wherein the clock generating circuit includes an output unit receiving the duty detection signals, selecting one of the duty detection signals and supplying a selected one of the duty detection signals to the first circuit unit. 
     
     
       21. A method for correcting a duty ratio of a clock provided by a delay locked loop, the method comprising:
 detecting in each of a plurality of duty detector circuits the duty ratio of the clock during a period of time different than other periods of time during which the remaining duty detector circuits detect the duty ratio of the clock;   latching duty detection signals by latching a duty detection signal at the output of each of the plurality of duty detector circuits following each respective period of time; and   adjusting the duty ratio of a delay line of the delay locked loop based on the latched duty detection signals from the plurality of duty detector circuits.    
     
     
       22. The method as claimed in claim 21 wherein the duty ratio of the delay line is adjusted to 50%.  
     
     
       23. The method as claimed in claim 21 wherein the duty ratio of the delay line is adjusted based on a majority of the latched duty detection signals.  
     
     
       24. The method as claimed in claim 21 wherein the delay locked loop comprises a rising edge delay line and a falling edge delay line, and the duty ratio of the clock is adjusted by changing the delay of the falling edge delay line.  
     
     
       25. The method as claimed in claim 21 wherein the periods of time are overlapping periods of time.  
     
     
       26. The method as claimed in claim 21 wherein the periods of time are equal duration periods of time.  
     
     
       27. The method as claimed in claim 21 wherein the periods of time comprise multiple clock cycle periods of time.  
     
     
       28. The method as claimed in claim 21 further comprising precharging each of the plurality of duty detector circuits prior to the detecting.  
     
     
       29. The method as claimed in claim 28 wherein each of the plurality of duty detector circuits comprises a capacitor which is charged to a predetermined voltage during the precharging.  
     
     
       30. The method as claimed in claim 28 wherein each of the plurality of duty detector circuits comprises first and second capacitors which are precharged to a predetermined voltage during the precharging.  
     
     
       31. The method as claimed in claim 30 wherein, during the detecting, the first capacitor is discharged while the clock has a high level and the second capacitor is discharged while the clock has a low level.  
     
     
       32. The method as claimed in claim 31 wherein the potential difference between the first capacitor and the second capacitor is detected to determine the duty ratio of the clock.