Ferroelectric random access memory and memory system

Abstract

In one embodiment, a non-volatile memory includes a first buffer that receives notification of power-down and outputs a first signal changed from a first value to a second value based on the notification, a first controlling unit that receives and outputs a command signal, a second controlling unit that generates and outputs a basic signal that has a third value when the command signal output from the first controlling unit indicates an active command and has a fourth value when the command signal indicates a command corresponding to a write back instruction or the first signal has the second value, a memory cell array in which memory cells are arrayed, and a sense amplifier circuit that reads data from the memory cell.

What is claimed is: 
     
       1. A non-volatile memory comprising:
 a first buffer configured to receive a notification of a power-down and output a first signal changed from a first value to a second value based on the notification; 
 a first controlling unit configured to receive and output a command signal; 
 a second controlling unit configured to generate and output a basic signal that has a third value when the command signal output from the first controlling unit indicates an active command and has a fourth value when the command signal indicates a command corresponding to a write back instruction or the first signal has the second value; 
 a memory cell array comprising memory cells; and 
 a sense amplifier circuit configured to read data from the memory cell. 
 
     
     
       2. The non-volatile memory according to  claim 1 , further comprising a third controlling unit configured to control write back to the memory cell from which the data are read so as to be performed after an elapse of a first time from the time the basic signal has the third value and when the basic signal has the fourth value. 
     
     
       3. The non-volatile memory according to  claim 1 , further comprising:
 a second buffer configured to generate and supply an inner clock signal and stop the supply of the inner clock signal with the change of the first signal from the first value to the second value; and 
 a third buffer configured to receive, hold, and output an address signal corresponding to data to be read or written, 
 wherein the sense amplifier circuit is configured to read data from the memory cell corresponding to the address signal. 
 
     
     
       4. The non-volatile memory according to  claim 1 , wherein the first buffer comprises a filter that removes noise. 
     
     
       5. The non-volatile memory according to  claim 2 , wherein the first time is longer than a time required for the sense amplifier circuit to read data from the memory cell. 
     
     
       6. The non-volatile memory according to  claim 1 , wherein the first buffer is configured to receive the notification via a CKE pin of a DDR interface. 
     
     
       7. The non-volatile memory according to  claim 1 , further comprising a power source stabilization capacitance as a backup power source that is configured to perform as a power supply for a second time when the first buffer receives the notification. 
     
     
       8. A non-volatile memory comprising:
 a first buffer configured to receive a notification of a power-down and output a first signal changed from a first value to a second value based on the notification; 
 a first controlling unit configured to receive and output a command signal and generate and output a second signal that is changed from a third value to a fourth value with the reception of a write command and is changed from the fourth value to the third value after an elapse of a first time from the reception of write data; 
 a delaying unit configured to generate and output a third signal that is changed from a fifth value to a sixth value with the change of the first signal from the second value to the first value and is changed from the sixth value to the fifth value when the first signal is changed from the first value to the second value and the second signal has the third value; 
 a second controlling unit configured to generate and output a basic signal that has a seventh value when the command signal output from the first controlling unit indicates an active command, and has an eighth value when the command signal indicates a command corresponding to a write back instruction or the third signal has the fifth value; 
 a memory cell array comprising memory cells; and 
 a sense amplifier circuit configured to read data from the memory cell. 
 
     
     
       9. The non-volatile memory according to  claim 8 , further comprising a third controlling unit configured to control write back to the memory cell from which the data are read to be performed after an elapse of a second time from the time the basic signal has the seventh value and when the basic signal has the eighth value. 
     
     
       10. The non-volatile memory according to  claim 8 , further comprising:
 a second buffer configured to generate and supply an inner clock signal and stop the supply of the inner clock signal with the change of the third signal from the sixth value to the fifth value; and 
 a third buffer configured to receive, hold, and output an address signal corresponding to data to be read or written, 
 wherein the sense amplifier circuit is configured to read data from the memory cell corresponding to the address signal. 
 
     
     
       11. The non-volatile memory according to  claim 8 , wherein the first buffer comprises a filter configured to remove noise. 
     
     
       12. The non-volatile memory according to  claim 8 , wherein the first buffer is configured to receive the notification via a CKE pin of a DDR interface. 
     
     
       13. The non-volatile memory according to  claim 8 , further comprising a power source stabilization capacitance as a backup power source that is configured to perform as a power supply for a third time when the first buffer receives the notification. 
     
     
       14. A memory system comprising:
 a non-volatile memory comprising a first buffer, a first controlling unit, a second controlling unit, a memory cell array comprising memory cells, and a sense amplifier circuit configured to read data from the memory cell array; and 
 a memory controller configured to output a first command signal corresponding to a read instruction and a second command signal corresponding to a write back instruction to the first controlling unit, and notify power-down to the first buffer when a source voltage is detected and the source voltage is less than a first value, 
 wherein the first buffer is configured to output a first signal changed from a first value to a second value based on the notification, and 
 the second controlling unit is configured to generate and output a basic signal that has a third value when the first controlling unit receives the first command signal and has a fourth value when the first controlling unit receives the second command signal or the first signal has the second value. 
 
     
     
       15. The memory system according to  claim 14 , further comprising a third controlling unit configured to control write back to the memory cell from which the data are read so as to be performed after an elapse of a second time from the time the basic signal has the third value and when the basic signal has the fourth value. 
     
     
       16. The memory system according to  claim 14 , wherein
 the memory controller is configured to output an address signal corresponding to data to be read or written, 
 the non-volatile memory further comprises
 a second buffer configured to generate and supply an inner clock signal and stop the supply of the inner clock signal with the change of the first signal from the first value to the second value, and 
 a third buffer is configured to receive, hold, and output the address signal, and 
 
 the sense amplifier circuit is configured to read data from the memory cell corresponding to the address signal. 
 
     
     
       17. The memory system according to  claim 14 , wherein the first buffer comprises a filter configured to remove noise. 
     
     
       18. The memory system according to  claim 15 , wherein the second time is longer than a time required for the sense amplifier circuit to read data from the memory cell. 
     
     
       19. The memory system according to  claim 14 , wherein the first buffer is configured to receive the notification via a CKE pin of a DDR interface. 
     
     
       20. The memory system according to  claim 14 , wherein the non-volatile memory further comprises a power source stabilization capacitance as a backup power source that performs power supply for a third time when the first buffer receives the notification. 
     
     
       21. A non-volatile memory comprising:
 a first buffer configured to change a first signal from a first value to a second value based on a notification signal;   a first controlling unit configured to receive and output a command signal synchronized with a clock;   an address buffer configured to receive and output an address signal synchronized with the clock;   a second controlling unit configured to output a basic signal having a third value or a fourth value, wherein the value of the basic signal is provided based upon the values of the address signal, the first signal, and the command signal, the basic signal having the fourth value when the first signal has the second value when the second controlling unit receives the command signal and the address signal;   a memory cell array comprising memory cells; and   a sense amplifier circuit configured to read data from the memory cell.    
     
     
       22. The non-volatile memory of claim 21, wherein the address signal designates a first part of the memory cell array.  
     
     
       23. The non-volatile memory of claim 22, wherein the data read from a first part of the memory cell array by the sense amplifier circuit is written back to the first part of the memory cell array when the basic signal has the fourth value.  
     
     
       24. The non-volatile memory of claim 22, wherein the first part of the memory cell array is not active once the basic signal has the fourth value.  
     
     
       25. The non-volatile memory of claim 22, wherein the memory cell array further comprises a second part, and the second part of the memory cell array is active once the basic signal has the fourth value.  
     
     
       26. The non-volatile memory of claim 21, wherein the memory cell array comprises a plurality of banks.  
     
     
       27. The non-volatile memory of claim 26, wherein the address signal designates a bank within the plurality of banks.  
     
     
       28. The non-volatile memory of claim 21, wherein the memory cell array is not accessed by the second controlling unit when the basic signal has the fourth value.  
     
     
       29. The non-volatile memory of claim 21, wherein the basic signal has the third value when the command signal output from the first controlling unit indicates an active command.  
     
     
       30. The non-volatile memory of claim 21, the basic signal has either of the third and fourth values when the first signal has the first value and has the fourth value when the first signal has the second value.  
     
     
       31. A non-volatile memory comprising:
 a first buffer configured to change a first signal from a first value to a second value based on a notification signal;   a first controlling unit configured to receive and output a command signal;   an address buffer configured to receive an address signal;   a second controlling unit configured to generate a basic signal based on the address signal, the first signal, and the command signal, the basic signal having a third value when the command signal output from the first controlling unit indicates an active command and a fourth value when the first signal has the second value;   a memory cell array comprising memory cells; and   a sense amplifier circuit configured to read data from the memory cell.    
     
     
       32. The non-volatile memory of claim 31, wherein the second controlling unit is further configured to output the basic signal having the fourth value when the first signal has the second value.  
     
     
       33. The non-volatile memory of claim 31, wherein the second controlling unit comprises a flip flop circuit and an AND circuit.  
     
     
       34. The non-volatile memory of claim 31, further comprising a third controlling unit configured to write to a memory cell when the basic signal has the third value.  
     
     
       35. The non-volatile memory of claim 34, wherein the third controlling unit is configured so as to only write to a memory cell when the first signal has the first value.  
     
     
       36. The non-volatile memory of claim 35, wherein the third controlling unit comprises an OR circuit.  
     
     
       37. The non-volatile memory of claim 31, further comprising a delay circuit interposed between the first buffer and the second controlling unit.  
     
     
       38. The non-volatile memory of claim 37, wherein the delay circuit is configured to output a delay signal based on an input from the first buffer and an input from the first controlling unit.  
     
     
       39. The non-volatile memory of claim 37, further comprising a third controlling unit configured to write to a memory cell after the first signal has changed from the first value to the second value.  
     
     
       40. The non-volatile memory of claim 31, further comprising a second buffer configured to output a second buffer signal in response to the first signal and a clock signal input thereto.