Phase-lock assistant circuitry

Abstract

Some embodiments regard a circuit comprising: a first circuit configured to lock a frequency of an output clock to a frequency of a reference clock; a second circuit configured to align an input signal to a phase clock of the output clock; a third circuit configured to use a first set of phase clocks of the output clock and a second set of phase clocks of the output clock to improve alignment of the input signal to the phase clock of the output clock; and a lock detection circuit configured to turn on the first circuit when the frequency of the output clock is not locked to the frequency of the reference clock; and to turn off the first circuit and to turn on the second circuit and the third circuit when the frequency of the output clock is locked to the frequency of the reference clock.

What is claimed is: 
     
       1. A method for a circuit having a phase lock assistant circuit that receives an input signal and a feedback clock signal having a first phase, a second phase, a third phase, a fourth phase, and fifth phase, and a sixth phase corresponding to a first phase clock, a second phase clock, a third phase clock, a fourth phase clock, a fifth phase clock, and a sixth phase clock, respectively, the method comprising:
 using the first phase clock, the third phase clock and the fifth phase clock to sample the input signal and generate a first relationship between the feedback clock signal and the input signal and a second relationship between the feedback clock signal and the input signal; 
 using the second phase clock, the fourth phase clock, and the sixth phase clock to sample the input signal and generate a third relationship between the feedback clock signal and the input signal and a fourth relationship between the feedback clock signal and the input signal; and 
 generating a fifth relationship between the feedback clock signal and the input signal based on the first relationship, the second relationship, the third relationship and the fourth relationship; 
 wherein the first phase, the second phase, the third phase, the fourth phase, the fifth phase and the sixth phase are in an order of phase degree. 
 
     
     
       2. The method of  claim 1  wherein the first phase, the second phase, the third phase, the fourth phase, the fifth phase and the sixth phase are at phases of 0°, 45°, 90°, 135°, 180°, are at 225°, respectively. 
     
     
       3. The method of  claim 1  wherein generating the fifth relationship comprises:
 generating the first relationship based on a result of the first phase clock sampling the input signal and a result of the third phase clock sampling the input signal; 
 generating the third relationship based on a result of the fifth phase clock sampling the input signal and the result of the third phase clock sampling the input signal; 
 generating the second relationship based on a result of the second phase clock sampling the input signal and a result of the fourth phase clock sampling the input signal; and 
 generating the fourth relationship based on a result of the sixth phase clock sampling the input signal and the result of the fourth phase clock sampling the input signal. 
 
     
     
       4. The method of  claim 1  further comprising:
 generating a first state of a signal if the second relationship and the fourth relationship occurs in a first clock cycle and the second relationship and the third relationship occur in a second clock cycle subsequent to the first clock cycle; and 
 generating a second state of the signal if the first relationship and the third relationship occur in a third clock cycle and the first relationship and the fourth relationship occur in a fourth cycle subsequent to the third clock cycle; 
 wherein the third clock cycle is subsequent to the second clock cycle. 
 
     
     
       5. The method of  claim 1  further comprising:
 generating a second state of a signal if the first relationship and the fourth relationship occur in a first clock cycle and the first relationship and the third relationship occur in a second clock cycle subsequent to the first clock cycle; and 
 generating a second state of the signal if the second relationship and the third relationship occur in a third clock cycle and the second relationship and the fourth relationship occur in a fourth cycle subsequent to the third clock cycle; 
 wherein the third clock cycle is subsequent to the second clock cycle. 
 
     
     
       6. A circuit comprising:
 a first circuit configured to lock a frequency of an output clock to a frequency of a reference clock; 
 a second circuit configured to align an input signal to a phase clock of the output clock; 
 a third circuit configured to use a first set of phase clocks of the output clock and a second set of phase clocks of the output clock to improve alignment of the input signal to the phase clock of the output clock; and 
 a lock detection circuit configured
 to turn on the first circuit when the frequency of the output clock is not locked to the frequency of the reference clock; and 
 to turn off the first circuit and to turn on the second circuit and the third circuit when the frequency of the output clock is locked to the frequency of the reference clock. 
 
 
     
     
       7. The circuit of  claim 6  wherein the third circuit comprises:
 a fourth circuit configured to receive the first set of phase clocks and the input signal and generate a first early signal indicating the output clock is earlier than the input signal and a first late signal indicating the output clock is later than the input signal; and 
 a fifth circuit configured to receive the second set of phase clocks and the input signal and generate a second early signal indicating the output clock is earlier than the input signal and a second late signal indicating the output clock is later than the input signal. 
 
     
     
       8. The circuit of  claim 7  wherein the third circuit further comprises:
 a sixth circuit configured to receive the first early signal, the first late signal, the second early signal, the second late signal, a clock in the first set of phase clocks to generate a first up signal corresponding to a first state of a first signal, a second up signal corresponding to the second state of the first signal, a first down signal corresponding to a first state of a second signal, and second down signal corresponding to a second state of the second signal; and 
 a seventh circuit configured to receive the first up signal, the second up signal, the first down signal, the second down signal, the clock in the first set of phase clocks, and a toggle signal generated by the fourth circuit to generate the first signal and the second signal. 
 
     
     
       9. The circuit of  claim 7  wherein
 the fourth circuit is configured to generate the first early signal when a first result of a first clock of the first set of phase clocks sampling the data is the same as a second result of a second clock of the first set of phase clocks sampling the data and generate the first late signal when the second result is the same as a third result of a third clock of the first set of phase clocks sampling the data, and 
 the fifth circuit is configured to generate the second early signal when a first result of a first clock of the second set of phase clocks sampling the data is the same as a second result of a second clock of the second set of phase clocks sampling the data and generate the first late signal when the second result of the second clock of the second set of phase clocks sampling the data is the same as a third result of a third clock of the second set of phase clocks sampling the data. 
 
     
     
       10. The circuit of  claim 6  wherein
 the first set of phase clocks includes a 0° phase clock, a 90° phase clock, and a 180° phase clock, and 
 the second set of phase clocks includes a 45° phase clock, a 135° phase clock, and a 225° phase clock. 
 
     
     
       11. The circuit of  claim 10  wherein
 the third circuit is configured to use the 0° phase clock, the 90° phase clock, and the 180° phase clock to generate a first early signal indicating the output clock is earlier than the input data and a first late signal indicating the output clock is later than the input data, and 
 the third circuit is configured to use the 45° phase clock, the 135° phase clock, and the 225° phase clock to generate a second early signal indicating the output clock is earlier than the input data and a second late signal indicating the output clock is later than the input data. 
 
     
     
       12. The circuit of  claim 11  wherein the third circuit is configured to use the first early signal, the first late signal, the second early signal, the second late signal, and the 0° phase clock to generate a first signal and a second signal used to improve the alignment of the input signal to the phase clock of the output clock. 
     
     
       13. The circuit of  claim 6  wherein the third circuit is configured to improve the alignment of the input signal to the phase clock of the output clock by increasing a frequency of the output clock if the output clock is slower than the input signal and by decreasing the frequency of the output clock if the output clock is faster than the input signal. 
     
     
       14. The circuit of  claim 13  further comprising a charge pump circuit configured to receive an output signal of the third circuit to increase the frequency of the output clock if the output clock is slower than the input signal and to decrease the frequency of the output clock if the output clock is faster than the input signal. 
     
     
       15. The circuit of  claim 14  further comprising a low pass filter circuit configured to receive an output signal of the charge pump circuit to increase the frequency of the output clock if the output clock is slower than the input signal and to decrease the frequency of the output clock if the output clock is faster than the input signal. 
     
     
       16. A circuit comprising:
 a first circuit configured to receive an input signal and first phase, third phase, and a fifth phase clocks of a clock, and generate a first early signal indicating the clock is earlier than the input signal and a first late signal indicating the clock is later than the input signal; 
 a second circuit configured to receive the input signal and second phase, fourth phase, and sixth phase clocks of the clock, and generate a second early signal indicating the clock is earlier than the input signal and a second late signal indicating the clock is later than the input signal; the first phase clock, the second phase clock, the third phase clock, the fourth phase clock, the fifth phase clock and the sixth phase clock are in an order of phase degree; and 
 a third circuit configured to receive the first early signal, the first late signal, the second early signal, the second late signal, and the first phase clock, and generate a first signal and a second signal that are used to align the input signal and the clock; 
 the first circuit is configured to use the first phase clock to sample the input signal and result in a first phase clock result, to use the third phase clock to sample the input signal and result in a third phase clock result, to use the fifth phase clock to sample the input signal and result in a fifth phase clock result, and to generate the first early signal when the first phase clock result is the same as the third phase clock result, and to generate the first late signal when the fifth phase clock result is the same as the third phase clock result; and 
 the second circuit is configured to use the second phase clock to sample the input signal and result in a second phase clock result, to use the fourth phase clock to sample the input signal and result in a fourth phase clock result, to use the sixth phase clock to sample the input signal and result in a sixth phase clock result, and to generate the second early signal when the second phase clock result is the same as the fourth phase lock result, and to generate the second late signal when the sixth phase clock result is the same as the fourth phase clock result. 
 
     
     
       17. The circuit of  claim 16  wherein the third circuit comprises:
 a fourth circuit configured to receive the first early signal, the first late signal, the second early signal, the second late signal, and the first phase clock and generate a first up signal, a second up signal, a first down signal, and a second down signal; and 
 a fifth circuit configured to receive the first up signal, the second up signal, the first down signal, the second down signal, the first phase clock, and a toggle signal generated by the first circuit, and generate the first signal and the second signal. 
 
     
     
       18. The circuit of  claim 16  wherein the first phase clock, the second phase clock, the third phase clock, the fourth phase clock, the fifth phase clock and the sixth phase clock are 0°, 45°, 90°, 135°, 180°, and 225° phase clocks, respectively. 
     
     
       19. The circuit of  claim 16  wherein the clock is a feedback clock. 
     
     
       20. A circuit comprising:
 a first circuit configured to lock a frequency of an output clock to a frequency of a reference clock;   a second circuit configured to align a phase clock of the output clock to an input signal;   a third circuit configured to use a first set of phase clocks of the output clock and a second set of phase clocks of the output clock to improve alignment of the input signal to the phase clock of the output clock; and   a lock detection circuit configured
 to turn on the first circuit when the frequency of the output clock is not locked to the frequency of the reference clock; and 
 to turn off the first circuit and to turn on the second circuit and the third circuit when the frequency of the output clock is locked to the frequency of the reference clock.  
   
     
     
       21. A circuit comprising:
 a first circuit configured to lock a frequency of an output clock to a frequency of a reference clock;   a second circuit configured to align a phase clock of the output clock to an input signal;   a third circuit configured to use a first set of phase clocks of the output clock and a second set of phase clocks of the output clock to improve alignment of the input signal to the phase clock of the output clock; and   a lock detection circuit configured to turn on the second circuit and the third circuit responsive to an output signal of the lock detection circuit.    
     
     
       22. A circuit comprising:
 a first circuit configured to receive an input signal and first phase, third phase, and fifth phase clocks of a clock, and generate a first early signal indicating the clock is earlier than the input signal and a first late signal indicating the clock is later than the input signal;   a second circuit configured to receive the input signal and second phase, fourth phase, and sixth phase clocks of the clock, and generate a second early signal indicating the clock is earlier than the input signal and a second late signal indicating the clock is later than the input signal; the first phase clock, the second phase clock, the third phase clock, the fourth phase clock, the fifth phase clock and the sixth phase clock are in an order of phase degree; and   a third circuit configured to receive the first early signal, the first late signal, the second early signal, and the second late signal, and at least one of the first, second, third, fourth, fifth, and sixth phase clock, and generate a first signal and a second signal that are used to align the input signal and the clock;   the first circuit being configured to:
 sample the input signal based on the first phase clock and generate a first phase clock result; 
 sample the input signal based on the third phase clock and generate a third phase clock result; 
 sample the input signal based on the fifth phase clock and generate a fifth phase clock result; and 
 generate the first early signal when the first phase clock result is the same as the third phase clock result, and generate the first late signal when the fifth phase clock result is the same as the third phase clock result; and 
   the second circuit being configured to:
 sample the input signal based on the second phase clock and generate a second phase clock result; 
 sample the input signal based on the fourth phase clock and generate a fourth phase clock result; 
 sample the input signal based on the sixth phase clock and generate a sixth phase clock result; and 
 generate the second early signal when the second phase clock result is the same as the fourth phase clock result, and generate the second late signal when the sixth phase clock result is the same as the fourth phase clock result.