Multiple write during simultaneous memory access of a multi-port memory device

Abstract

A memory system may provide for a successful write of a multi-port memory cell (e.g., dual-port 2WR SRAM cell) when it is simultaneously accessed by more than one port. This multi-port memory cell may include at least two independent accesses to the memory cell, where each access may be controlled by an independent wordline signal. Each port may have an independent pair of bitlines. Multiple write circuitry (e.g., double write circuitry) may enable the write driver to drive the input data to more than one pair of bitlines simultaneously.

What is claimed is: 
     
       1. A semiconductor memory, comprising:
 a first set of bit line pairs, wherein a respective bit line pair of the first set of bit line pairs is connected to one or more respective first ports of one or more respective multi-port memory cells; 
 a second set of bit line pairs, wherein a respective bit line pair of the second set of bit line pairs is connected to respective second ports of one or more respective one of the multi-port memory cells; and 
 at least one pair of switch components, wherein each switch component in the pair of switch components is configured to connect a wire from the first set of bit line pairs to a wire from the second set of bit line pairs, wherein the wire from the first set of bit line pairs and the wire from the second set of bit line pairs are both connected to a same one or more multi-port memory cells of the multi-port memory cells. 
 
     
     
       2. The semiconductor memory as in  claim 1 , wherein the switch components are transmission gates. 
     
     
       3. The semiconductor memory as in  claim 1 , wherein the switch components are pass transistors. 
     
     
       4. The semiconductor memory as in  claim 1 , further comprising an address comparator, wherein one or more of the switch components are enabled by the address comparator. 
     
     
       5. The semiconductor memory as in  claim 1 , further comprising:
 at least a third set of bit line pairs; and 
 at least one further pair of switch components, wherein each switch component of the at least one further pair of switch components is configured to connect a wire from the at least a third set of bit line pairs to a wire from a different set of bit line pairs. 
 
     
     
       6. A semiconductor memory comprising:
 a first access port comprising a first set of bit line pairs; 
 a second access port comprising a second set of bit line pairs; and 
 a conflict detector, 
 wherein said first access port is configured to drive lines among the first set of bit line pairs and said second access port is configured to drive lines among the second set of bit line pairs, and 
 wherein said first access port is further configured to drive one or more lines among the second set of bit line pairs if a conflict is detected by the conflict detector. 
 
     
     
       7. The semiconductor memory as in  claim 6 , wherein the conflict detector is configured to compare portions of address inputs associated with the first access port and the second access port. 
     
     
       8. The semiconductor memory as in  claim 6 , further comprising:
 a third access port comprising a third set of bitline pairs, wherein the third access port is configured to drive lines among the third set of bitline pairs, and wherein the third access port is further configured to drive one or more lines among the first set of bitline pairs or the second set of bitline pairs if a conflict is detected by the conflict detector. 
 
     
     
       9. The semiconductor memory as in  claim 8 , wherein the conflict detector is configured to compare portions of address inputs associated with the first access port, the second access port, and/or the third access port. 
     
     
       10. A method for writing a semiconductor memory comprising two or more ports, wherein each port includes an address input and a data input port, and at least one memory array, the method comprising:
 comparing addresses defined by the address inputs to determine if different ports are accessing one or more memory locations of a same word in the memory array; and 
 if the different ports are accessing one or more memory locations of the same word in the memory array, driving the same data onto the data input ports of the different ports accessing the same word of the memory array. 
 
     
     
       11. The method as in  claim 10 , wherein driving the same data onto the data input ports of the different ports comprises forming one or more electrical connections between corresponding elements of the data input ports of the different ports to enable the data input ports of the different ports to write the same data to the one or more memory locations of the same word. 
     
     
       12. The method as in  claim 11 , wherein forming one or more electrical connections comprises selectively enabling a circuit element to provide the connection. 
     
     
       13. The method as in  claim 12 , wherein selectively enabling comprises:
 determining at a particular port if the port is attempting to write to a memory location in the same word of the memory array in which at least one other port is attempting to write to a memory location; and 
 enabling the circuit element to provide the connection, wherein the circuit element corresponds to the memory location to which the particular port is attempting to write.