USRE46490EActiveUtility

Semiconductor device

52
Assignee: TOSHIBA KKPriority: Nov 29, 2010Filed: Jul 16, 2015Granted: Jul 25, 2017
Est. expiryNov 29, 2030(~4.4 yrs left)· nominal 20-yr term from priority
Inventors:Toshiki Seshita
H03K 3/00H10D 86/201H03K 3/02
52
PatentIndex Score
0
Cited by
6
References
33
Claims

Abstract

According to one embodiment, a semiconductor device includes an interface, a power supply, a driver, and a switch section. The interface includes a first MOSFET and converts a terminal switch signal of input serial data into parallel data. The first MOSFET is provided on the SOI substrate and has a back gate in a floating state. The power supply includes a second MOSFET and generates an ON potential higher than a potential of a power supply to be supplied to the interface. The second MOSFET is provided on the SOI substrate and has a back gate connected to a source. The driver includes a third MOSFET and outputs a control signal for controlling the ON potential to be in a high level according to the parallel data. The third MOSFET is provided on the SOI substrate and has a back gate connected to a source.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A semiconductor device, comprising:
 an interface including a first MOSFET and converting a terminal switch serial input signal of input serial data into parallel data signals, the first MOSFET being provided on an SOI a silicon-on-insulator substrate and having a back gate in a floating state and; 
 a power supply including a second MOSFET and generating an ON output potential that is higher than a potential of a power supply potential to be supplied to the interface, the second MOSFET being provided on an SOI the silicon-on-insulator substrate and having a back gate connected to a source of the second MOSFET; 
 a driver including a third MOSFET and outputting a control signal for controlling the ON potential to be in a high level according to the parallel data signals, the third MOSFET provided on an SOI the silicon-on-insulator substrate and having a back gate connected to a source of the third MOSFET; and 
 a switch section provided on the SOI silicon-on-insulator substrate and switching connection connections between a plurality of terminals by inputting according to the control signal. 
 
     
     
       2. The device according to  claim 1 ,
 wherein a gate length of the second MOSFET is longer than that a gate length of the first MOSFET. 
 
     
     
       3. The device according to  claim 1 ,
 wherein a gate length of the third, MOSFET is longer than that a gate length of the first MOSFET. 
 
     
     
       4. The device according to  claim 1 ,
 wherein an absolute value of a threshold voltage of the second MOSFET is larger than that of a threshold voltage of the first MOSFET. 
 
     
     
       5. The device according to  claim 1 ,
 wherein an absolute value of a threshold voltage of the third MOSFET is larger than that of a threshold voltage of the first MOSFET. 
 
     
     
       6. The device according to  claim 1 , further comprising:
 a decoder decoding the parallel data. 
 
     
     
       7. The device according to  claim 1 ,
 wherein the back gate of the second MOSFET is drawn to both on two sides of the source in a vertical direction to the SOI substrate of the second MOSFET, the two sides of the source of the second MOSFET being spaced from each other in a direction parallel to a gate width direction of the second MOSFET. 
 
     
     
       8. The device according to  claim 7 ,
 wherein the second MOSFET is formed in an H-shape in the vertical direction to the SOI substrate. 
 
     
     
       9. The device according to  claim 1 ,
 wherein the back gate of the third MOSFET is drawn to both on two sides of the source in a vertical direction to the SOI substrate of the third MOSFET, the two sides of the source of the third MOSFET being spaced from each spaced from each other in a direction parallel to a gate width direction of the third MOSFET. 
 
     
     
       10. The device according to  claim 9 ,
 wherein the third MOSFET is formed in an H-shape in the vertical direction to the SOI substrate. 
 
     
     
       11. The device according to  claim 1 ,
 wherein the third MOSFET has the same planar layout shape as the second MOSFET. 
 
     
     
       12. The device according to  claim 1 ,
 wherein the first MOSFET has a lower breakdown voltage than the second MOSFET. 
 
     
     
       13. The device according to  claim 1 ,
 wherein the first MOSFET has a lower breakdown voltage than the third MOSFET. 
 
     
     
       14. The device according to  claim 1 ,
 wherein the first MOSFET has a smaller layout area than the second MOSFET. 
 
     
     
       15. The device according to  claim 1 ,
 wherein the first MOSFET has a smaller layout area than the third MOSFET. 
 
     
     
       16. The device according to  claim 1 , further comprising:
 a power supply pad provided on both sides of the interface on the SOI silicon-on-insulator substrate on a first side of the interface, the power supply pad for supplying power to the interface; and 
 a ground pad provided on the silicon-on-insulator substrate on a second side of the interface opposite the first side. 
 
     
     
       17. A semiconductor device, comprising:
 an interface provided on a silicon-on-insulator substrate and configured to convert serial data into parallel data, the interface including a first MOSFET having a back gate with a floating potential;   a first power supply provided on the silicon-on-insulator substrate and configured to generate a first potential that is greater than a second potential, the second potential being supplied to the interface by a second power supply, the first power supply including a second MOSFET having a back gate connected to a source of the second MOSFET;   a driver provided on the silicon-on-insulator substrate and including a third MOSFET having a back gate connected to a source of the third MOSFET, the driver configured to generate a plurality of control signals based on the first potential according to the parallel data; and   a switch section provided on the silicon-on-insulator substrate and including a plurality of terminals, the switch section configured to switch connections among the plurality of terminals according to the plurality of the control signals.    
     
     
       18. The device according to claim 17, wherein
 a gate length of the second MOSFET is longer than a gate length of the first MOSFET.    
     
     
       19. The device according to claim 17, wherein
 a gate length of the third MOSFET is longer than a gate length of the first MOSFET.    
     
     
       20. The device according to claim 17, wherein
 an absolute value of a threshold voltage of the second MOSFET is larger than an absolute value of a threshold voltage of the first MOSFET.    
     
     
       21. The device according to claim 17, wherein
 an absolute value of a threshold voltage of the third MOSFET is larger than an absolute value of a threshold voltage of the first MOSFET.    
     
     
       22. The device according to claim 17, further comprising:
 a decoder configured to decode the parallel data and supply decoded data to the driver.    
     
     
       23. The device according to claim 17, wherein
 the first MOSFET has a lower breakdown voltage than the second MOSFET.    
     
     
       24. The device according to claim 17, wherein
 the first MOSFET has a lower breakdown voltage than the third MOSFET.    
     
     
       25. The device according to claim 17, wherein
 the first MOSFET has a smaller layout area than the second MOSFET.    
     
     
       26. The device according to claim 17, wherein
 the first MOSFET has a smaller layout area than the third MOSFET.    
     
     
       27. The device according to claim 17, further comprising:
 a power supply pad provided on the silicon-on-insulator substrate on a first side of the interface, the power supply pad for supplying power to the interface; and   a ground pad provided on the silicon-on-insulator substrate on a second side of the interface opposite the first side.    
     
     
       28. The device according to claim 17, wherein
 the interface, the first power supply, the driver, and the switch section are included in a radio frequency switch device.    
     
     
       29. The device according to claim 28, wherein
 the plurality of terminals includes an antenna terminal and a plurality of radio frequency input/output terminals, and the switch section is configured to switch connections among the plurality of terminals for transmitting and receiving radio frequency signals by the antenna terminal.    
     
     
       30. The device according to claim 28, wherein
 a gate length of the second MOSFET is longer than a gate length of the first MOSFET.    
     
     
       31. The device according to claim 28, wherein
 a gate length of the third MOSFET is longer than a gate length of the first MOSFET.    
     
     
       32. The device according to claim 28, wherein
 the first MOSFET has a smaller layout area than the second MOSFET.    
     
     
       33. The device according to claim 28, wherein
 the first MOSFET has a smaller layout area than the third MOSFET.

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