Reducing energy consumption when applying body bias to substrate having sets of NAND strings

Abstract

Body bias can be applied to optimize performance in a non-volatile storage system. Body bias can be set in an adaptive manner to reduce an error count of an error correcting and/or detecting code when reading data from non-volatile storage elements. Also, a body bias level can be increased or decreased as a number of programming cycles increases. Also, body bias levels can be set and applied separately for a chip, plane, block and/or page. A body bias can be applied to a first set of NAND strings for which operations are being performed by controlling a first voltage provided to a source side of the first set of NAND strings and a second voltage provided to a p-well. A source side of a second set of NAND strings for which operations are not being performed is floated or receives a fixed voltage.

What is claimed is: 
     
       1. A method for operating non-volatile storage, comprising, during a first time interval:
 performing operations on a first set of NAND strings; 
 biasing the first set of NAND strings by controlling a first voltage provided to a source side of the first set of NAND strings via a first source voltage supply line and a second voltage provided to a p-well region on which the first set of NAND strings are formed, at least in part; and 
 floating a source side of a second set of NAND strings which are formed, at least in part, on the p-well region by floating a second source voltage supply line for the second set of NAND strings, wherein operations comprising at least one of reading operations and or verifying operations, are not performed on the second set of NAND strings during the first time interval, wherein the first voltage is applied to the first source voltage supply line at a same time as the second source voltage supply line is floated. 
 
     
     
       2. The method of  claim 1 , wherein:
 the first voltage is provided via a first source voltage supply line.   
     
     
       3. The method of  claim 1 , wherein:
 the floating the source side of the second set of NAND strings comprises floating a second source voltage supply line for the second set of NAND strings.   
     
     
       4. The method of  claim 1 , wherein:
 a difference between the first and second voltages is based on a desired bias level. 
 
     
     
       5. The method of  claim 1 , wherein:
 the operations performed on the first set of NAND strings comprise at least one of reading operations and or verifying operations. 
 
     
     
       6. The method of  claim 1 , further comprising, during a second time interval outside the first time interval:
 performing operations on the second set of NAND strings; 
 biasing the second set of NAND strings by controlling a voltage provided to the source side of the second set of NAND strings and a voltage provided to the p-well region; and 
 floating the source side of the first set of NAND strings, where operations comprising at least one of reading operations and or verifying operations, are not performed on the first set of NAND strings during the second time interval. 
 
     
     
       7. A non-volatile storage system, comprising:
 first and second sets of NAND strings formed, at least in part, on a p-well region of a substrate; and 
 one or more control circuits in communication with the first and second sets of NAND strings, the one or more control circuits, during a first time interval: (a) perform operations on the first set of NAND strings, (b) bias the first set of NAND strings by controlling a first voltage provided to a source side of the first set of NAND strings via a first source voltage supply line and a second voltage provided to the p-well region, and (c) floating float a source side of the second set of NAND strings by floating a second source voltage supply line for the second set of NAND strings, wherein the first voltage is provided to the first source voltage supply line at a same time as the second source voltage supply line is floated, and during a second time interval outside the first time interval, the one or more control circuits: (d) perform operations on the second set of NAND strings, (e) bias the second set of NAND strings by controlling a voltage provided to the source side of the second set of NAND strings via the second source voltage supply line and a voltage provided to the p-well region, and (f) float the source side of the first set of NAND strings by floating the first source voltage supply line, where wherein the second voltage is provided to the second source voltage supply line at a same time as the first source voltage supply line is floated, and operations comprising at least one of reading operations and or verifying operations are not performed on the first set of NAND strings during the second time interval. 
 
     
     
       8. The non-volatile storage system of  claim 7 , wherein:
 operations comprising at least one of reading operations and or verifying operations, are not performed on the second set of NAND strings during the first time interval. 
 
     
     
       9. The non-volatile storage system of  claim 7 , wherein:
 the first voltage is provided via a first source voltage supply line.   
     
     
       10. The non-volatile storage system of  claim 7 , wherein:
 the one or more control circuits float the source side of the second set of NAND strings by floating a second source voltage supply line for the second set of NAND strings.   
     
     
       11. The non-volatile storage system of  claim 7 , wherein:
 a difference between the first and second voltages is based on a desired bias level. 
 
     
     
       12. The non-volatile storage system of  claim 7 , wherein:
 the operations performed on the first set of NAND strings comprise at least one of reading operations and or verifying operations. 
 
     
     
       13. The method of claim 1, wherein:
 the first and second sets of NAND strings comprises storage elements in a three-dimensional array of storage elements.   
     
     
       14. The non-volatile storage system of claim 7, wherein:
 the first and second sets of NAND strings comprises storage elements in a three-dimensional array of storage elements.