USRE46550EActiveUtility
16k mode interleaver in a digital video broadcasting (DVB) standard
Est. expiryOct 30, 2027(~1.3 yrs left)· nominal 20-yr term from priority
H04L 1/0071H04L 1/0057H04L 27/2647H04L 27/2601H04L 27/2649H04L 27/2626H04L 5/0044H04N 7/24G06F 7/584H03M 13/6552H03M 13/2785H03M 13/276H03M 13/2739H03M 13/27H04H 40/18
81
PatentIndex Score
2
Cited by
79
References
67
Claims
Abstract
A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.
Claims
exact text as granted — not AI-modifiedThe invention claimed is:
1. A data processing apparatus configured to map input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol, the data processing apparatus comprising:
an interleaver configured to read-into a memory the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals, and to read-out of the memory the data symbols for the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on the sub-carrier signals, and
an address generator configured to generate the set of addresses, an address being generated for each of the input symbols to indicate one of the sub-carrier signals onto which the data symbol is to be mapped, the address generator comprising:
a linear feedback shift register including a predetermined number of register stages and being configured to generate a pseudo-random bit sequence in accordance with a generator polynomial,
a permutation circuit configured to receive the content of the shift register stages and to permute the bits present in the register stages in accordance with a permutation order to form an address of one of the OFDM subcarriers, and
a control unit configured in combination with an address check circuit to re-generate an address when a generated address exceeds a predetermined maximum valid address, wherein
the predetermined maximum valid address is approximately sixteen thousand,
the linear feedback shift register has thirteen register stages with a generator polynomial for the linear feedback shift register of R i ′[ 12 ]=R i−1 ′[ 0 ]⊕ R i−1 ′[ 1 ]⊕ R i−1 ′[ 4 ]⊕ R i−1 ′[ 5 ]⊕ R i−1 ′[ 9 ]⊕ R i−1 ′[ 11 ], and the permutation order forms, with an additional bit, a fourteen bit address R i [n] for the i-th data symbol from the bit present in the n-th register stage R i ′[n] in accordance with a code defined by the table:
R′ i bit positions
12
11
10
9
8
7
6
5
4
3
2
1
0
R i bit
8
4
3
2
0
11
1
5
12
10
6
7
9
positions.
2. The data processing apparatus as claimed in claim 1 , wherein the predetermined maximum valid address is a value substantially between twelve thousand and sixteen thousand three hundred and eighty four.
3. The data processing apparatus as claimed in claim 1 , wherein the OFDM symbol includes pilot sub-carriers, which are arranged to carry known symbols, and the predetermined maximum valid address depends on a number of the pilot sub-carrier symbols present in the OFDM symbol.
4. The data processing apparatus as claimed in claim 1 , wherein the interleaver memory is configured to effect the mapping of the input data symbols onto the sub-carrier signals for even OFDM symbols by reading in the data symbols according to the set of addresses generated by the address generator and reading out in a sequential order, and for odd OFDM symbols by reading in the symbols into the memory in a sequential order and reading out the data symbols from the memory in accordance with the set of addresses generated by the address generator.
5. The data processing apparatus as claimed claim 1 , wherein the permutation circuit is configured to change the permutation code, which permutes the order of the bits of the register stages to form the addresses from one OFDM symbol to another.
6. The data processing apparatus as claimed in claim 5 , wherein the permutation circuit is configured to cycle through a sequence of different permutation codes for successive OFDM symbols.
7. The data processing apparatus as claimed in claim 6 , wherein the sequence of permutation codes comprises two permutation codes, which are
R′ i bit positions
12
11
10
9
8
7
6
5
4
3
2
1
0
R i bit
8
4
3
2
0
11
1
5
12
10
6
7
9
positions
and
R′ i bit positions
12
11
10
9
8
7
6
5
4
3
2
1
0
R i bit
7
9
5
3
11
1
4
0
2
12
10
8
6
positions.
8. The data processing apparatus as claimed in claim 5 , wherein for both odd OFDM symbols and even OFDM symbols the interleaver is configured to read-into the memory the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals in a sequential order, and to read-out of the memory the data symbols for the OFDM sub-carriers to effect the mapping according to the set of addresses generated by the address generator.
9. A transmitter for transmitting data using Orthogonal Frequency Division Multiplexing (OFDM), the transmitter including the data processing apparatus according to claim 1 .
10. The transmitter as claimed in claim 9 , wherein the transmitter is configured to transmit data in accordance with a Digital Video Broadcasting standard such as including the Digital Video Broadcasting-Terrestrial standard, the Digital Video Broadcasting-Handheld standard, or the Digital Video Broadcasting-Terrestrial2 standard.
11. A method of mapping input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol, the method comprising;
reading-into a memory the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals,
reading-out of the memory the data symbols for the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on the sub-carrier signals, and
generating the set of addresses, an address being generated for each of the input symbols to indicate one of the sub-carrier signals onto which the data symbol is to be mapped, the generating the set of addresses comprising:
using a linear feedback shift register including a predetermined number of register stages to generate a pseudo-random bit sequence in accordance with a generator polynomial,
using a permutation circuit configured to receive the content of the shift register stages to permute the bits present in the register stages in accordance with a permutation order to form an address, and
re-generating an address when a generated address exceeds a predetermined maximum valid address, wherein
the predetermined maximum valid address is approximately sixteen thousand,
the linear feedback shift register has thirteen register stages with a generator polynomial for the linear feedback shift register of R i ′[ 12 ]=R i−1 ′[ 0 ]⊕ R i−1 ′[ 1 ]⊕ R i−1 ′[ 4 ]⊕ R i−1 ′[ 5 ]⊕ R i−1 ′[ 9 ]⊕ R i−1 ′[ 11 ], and the permutation order forms, with an additional bit, a fourteen bit address R i [n] for the i-th data symbol from the bit present in the n-th register stage R i ′[n] in accordance with a code defined by the table:
R′ i bit positions
12
11
10
9
8
7
6
5
4
3
2
1
0
R i bit
8
4
3
2
0
11
1
5
12
10
6
7
9
positions.
12. The method as claimed in claim 11 , wherein the predetermined maximum valid address is a value substantially between twelve thousand and sixteen thousand three hundred and eighty four.
13. The method as claimed in claim 11 , wherein the OFDM symbol includes pilot sub-carriers, which are arranged to carry known symbols, and the predetermined maximum valid address depends on a number of the pilot sub-carrier symbols present in the OFDM symbol.
14. The method as claimed in claim 11 , wherein the using a permutation circuit to receive the content of the shift register stages and permuting the bits present in the register stages in accordance with a permutation code to form an address, includes changing the permutation code, which permutes the order of the bits of the register stages to form the addresses, from one OFDM symbol to another.
15. The method as claimed in claim 14 , wherein the changing the permutation code, which permutes the order of the bits of the register stages to form the addresses, from one OFDM symbol to another includes cycling through a sequence of different permutation codes for successive OFDM symbols.
16. The method as claimed in claim 15 , wherein the sequence of permutation codes comprises two permutation codes, which are
R′ i bit positions
12
11
10
9
8
7
6
5
4
3
2
1
0
R i bit
8
4
3
2
0
11
1
5
12
10
6
7
9
positions
and
R′ i bit positions
12
11
10
9
8
7
6
5
4
3
2
1
0
R i bit
7
9
5
3
11
1
4
0
2
12
10
8
6
positions.
17. The method as claimed in claim 14 , wherein the reading-into the memory the predetermined number of data symbols from the OFDM sub-carrier signals, includes for both odd OFDM symbols and even OFDM symbols reading in the data symbols into the memory the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals in a sequential order, and the reading-out of the memory the data symbols for the OFDM sub-carriers, includes for both odd OFDM symbols and even OFDM symbols reading-out of the memory the data symbols for the OFDM sub-carriers to effect the mapping according to addresses generated by the address generator.
18. A method of transmitting data symbols via a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol, the method comprising;
receiving a predetermined number of data symbols for mapping onto the predetermined number of sub-carrier signals,
reading-into a memory the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals,
reading-out of the memory the data symbols for the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on the sub-carrier signals, and
generating the set of addresses, an address being generated for each of the input symbols to indicate one of the sub-carrier signals onto which the data symbol is to be mapped, the generating the set of addresses comprising:
using a linear feedback shift register including a predetermined number of register stages to generate a pseudo-random bit sequence in accordance with a generator polynomial,
using a permutation circuit configured to receive the content of the shift register stages to permute the bits present in the register stages in accordance with a permutation order to form an address, and
re-generating an address when a generated address exceeds a predetermined maximum valid address, wherein
the predetermined maximum valid address is approximately sixteen thousand,
the linear feedback shift register has thirteen register stages with a generator polynomial for the linear feedback shift register of R i ′[ 12 ]=R i−1 ′[ 0 ]⊕ R i−1 ′[ 1 ]⊕ R i−1 ′[ 4 ]⊕ R i−1 ′[ 5 ]⊕ R i−1 ′[ 9 ]⊕ R i−1 ′[ 11 ], and the permutation order forms, with an additional bit, a fourteen hit address R i [n] for the i-th data symbol from the bit present in the n-th register stage R i ′[n] in accordance with a code defined by the table:
R′ i bit positions
12
11
10
9
8
7
6
5
4
3
2
1
0
R i bit
8
4
3
2
0
11
1
5
12
10
6
7
9
positions.
19. An address generator for use with transmission of data symbols interleaved onto sub-carriers of an Orthogonal Frequency Division Multiplexed symbol, the address generator being configured to generate a set of addresses, each address being generated for each of the data symbols to indicate one of the sub-carrier signals onto which the data symbol is to be mapped, the address generator comprising:
a linear feedback shift register including a predetermined number of register stages and being configured to generate a pseudo-random bit sequence in accordance with a generator polynomial,
a permutation circuit configured to receive the content of the shift register stages and to permute the bits present in the register stages in accordance with a permutation order to form an address, and
a control unit configured in combination with an address check circuit to re-generate an address when a generated address exceeds a predetermined maximum valid address, wherein
the predetermined maximum valid address is approximately sixteen thousand,
the linear feedback shift register has thirteen register stages with a generator polynomial for the linear feedback shift register of R i ′[ 12 ]=R i−1 ′[ 0 ]⊕ R i−1 ′[ 1 ]⊕ R i−1 ′[ 4 ]⊕ R i−1 ′[ 5 ]⊕ R i−1 ′[ 9 ]⊕ R i−1 ′[ 11 ], and the permutation order forms, with an additional bit, a fourteen bit address R i [n] for the i-th data symbol from the bit present in the n-th register stage R i ′[n] in accordance with the table:
R′ i bit positions
12
11
10
9
8
7
6
5
4
3
2
1
0
R i bit
8
4
3
2
0
11
1
5
12
10
6
7
9
positions.
20. A data processing apparatus configured to map input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol, the data processing apparatus comprising:
an interleaver configured to read-into a memory a predetermined number of data symbols for mapping onto the OFDM sub-carrier signals, and to read-out of the memory the data symbols for the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on the sub-carrier signals, and an address generator configured to generate the set of addresses, an address being generated for each of the input symbols to indicate one of the sub-carrier signals onto which the data symbol is to be mapped, the address generator comprising: a linear feedback shift register including a predetermined number of register stages and being configured to generate a pseudo-random bit sequence in accordance with a generator polynomial, and an address check circuit configured to re-generate an address when a generated address exceeds a predetermined maximum valid address, wherein the predetermined maximum valid address is approximately sixteen thousand, the linear feedback shift register has thirteen register stages with a generator polynomial for the linear feedback shift register of R′ i [12]=R′ i −1[0]⊕ R′ i −1[1]⊕ R′ i −1[4]⊕ R′ i −1[5]⊕ R i −1[9]⊕ R′ i −1[11], that is configured to form, with an additional bit, a fourteen bit address R i [n] for the i-th data symbol from the bit present in the n-th register stage R′ i [n] and wherein the address generator comprises an offset generator configured to add an offset to the formed 14 bit address.
21. The data processing apparatus as claimed in claim 20, wherein the offset generator is configured to add the offset to the formed fourteen bit address modulo the predetermined number of sub-carrier symbols.
22. The data processing apparatus as claimed in claim 20, wherein the offset generator generates the offset using another address generator.
23. The data processing apparatus a claimed in claim 22, wherein the another address generator forms a 14 bit address using a toggle value.
24. The data processing apparatus as claimed in claim 22, wherein the predetermined number of sub-carrier signals is determined in accordance with one of a plurality of operating modes and the other address generator used by the offset generator to generate the offset is an address generator for one of the plurality of operating modes.
25. The data apparatus as claimed in claim 24, wherein the other address generator is the address generator for the 32k operating mode.
26. The data processing apparatus as claimed in claim 20, wherein the OFDM symbol includes pilot sub-carriers which are arranged to carry known symbols, and the predetermined maximum valid address depends on a number of the sub-carrier pilot symbols present in the OFDM symbol.
27. The data processing apparatus as claimed in claim 20, wherein the predetermined maximum valid address is a value substantially between twelve thousand and sixteen thousand three hundred and eighty four.
28. The data processing apparatus as claimed in claim 20, where the address generator comprises a permutation circuit configured to receive the content of the shift register stages and to permute the bits present in the register stages in accordance with a permutation order to form an address of one of the OFDM sub-carriers.
29. The data processing apparatus as claimed in claim 28, wherein the address generator comprises a control circuit which is configured to re generate an address in combination with the address check circuit.
30. The data processing apparatus according to claim 29, wherein the linear feedback shift register is configured to generate the fourteen bit address in accordance with a code defined by the table:
R′ i bit positions
12
11
10
9
8
7
6
5
4
3
2
1
0
R i bit
8
4
3
2
0
11
1
5
12
10
6
7
9
positions.
31. The data processing apparatus as claimed in claim 29, wherein the offset generator is configured to add the offset to the formed fourteen bit address modulo the predetermined number of sub-carrier symbols.
32. The data processing apparatus as claimed in claim 29, wherein the offset generator generates the offset using another address generator.
33. The data processing apparatus as claimed in claim 32, wherein the predetermined number of sub-carrier signals is determined in accordance with one of a plurality of operating modes and the other address generator used by the offset generator to generate the offset is an address generator for one of the plurality of operating modes.
34. The data processing apparatus as claimed in claim 29, wherein the permutation circuit is arranged to change a permutation code, which permutes the order of the bits of the register stages to form the addresses from one OFDM symbol to another.
35. The data processing apparatus as claimed in claim 32, wherein the another address generator is an address generator configured to generate addresses having a predetermined maximum value of thirty two thousand seven hundred and sixty eight.
36. The data processing apparatus as claimed in claim 33, wherein the other address generator is the address generator for the 32k operating mode.
37. A transmitter for transmitting data using Orthogonal Frequency division Multiplexing (OFDM), the transmitter including the data processing apparatus of claim 20.
38. A method of mapping input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol, the method comprising;
reading-into a memory a predetermined number of data symbols for mapping onto the OFDM sub-carrier signals, reading-out of the memory the data symbols for the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on the sub-carrier signals, and generating the set of addresses, an address being generated for each of the input symbols to indicate one of the sub-carrier signals onto which the data symbol is to be mapped, the generating the set of addresses comprising: using a linear feedback shift register including a predetermined number of register stages to generate a pseudo-random bit sequence in accordance with a generator polynomial, re-generating an address when a generated address exceeds a predetermined maximum valid address, wherein the predetermined maximum valid address is approximately sixteen thousand, the linear feedback shift register has thirteen register stages with a generator polynomial for the linear feedback shift register of R′ i [12]=R′ i −1[0]⊕ R′ i −1[1]⊕ R′ i −1[4]⊕ R′ i −1[5]⊕ R i −1[9]⊕ R′ i −1[11], and the permutation order forms, with an additional bit, a fourteen bit address R i [n] for the i-th data symbol from the bit present in the n-th register stage R′ i [n] and adding by offset generator circuitry an offset to the formed 14 bit address.
39. The method as claimed in claim 38, wherein the adding the offset comprises adding the offset to the formed fourteen bit address modulo the predetermined number of sub-carrier symbols.
40. The method as claimed in claim 39, wherein the adding an offset comprises generating addresses using a differently configured linear feedback shift register of an address generator to form, with a toggle value, 14 bit addresses.
41. The method as claimed in claim 39, wherein the predetermined number of sub-carrier signals is determined in accordance with one of a plurality of operating modes and the adding the offset comprises generating an address for another of the plurality of operating modes using a differently configured linear feedback shift register of an address generator.
42. The method as claimed in claim 39, wherein the OFDM symbol includes pilot sub-carriers which are arranged to carry known symbols, and the predetermined maximum valid address depends on a number of the sub-carrier pilot symbols present in the OFDM symbol.
43. The method as claim in claim 39, wherein the predetermined maximum valid address is a value substantially between twelve thousand and sixteen thousand three hundred and eighty four.
44. The method as claimed in claim 41, wherein the another operating mode is the 32k operating mode.
45. The method as claimed in claim 39, comprising using a permutation circuit configured to receive the content of the shift register stages to permute the bits present in the register stages in accordance with a permutation order to form an address.
46. The method according to claim 45, wherein the linear feedback shift register generates the fourteen bit address in accordance with a code defined by the table:
R′ i bit positions
12
11
10
9
8
7
6
5
4
3
2
1
0
R i bit
8
4
3
2
0
11
1
5
12
10
6
7
9
positions.
47. The method as claimed in claim 45, wherein the adding the offset comprises adding the offset to the formed fourteen bit address modulo the predetermined number of sub-carrier symbols.
48. The method as claimed in claim 45, wherein the predetermined number of sub-carrier signals is determined in accordance with one of a plurality of operating modes and the adding the offset comprises generating an address for another of the plurality of operating modes.
49. The method as claimed in claim 45, comprising changing a permutation code, which permutes the order of the bits of the register stages to form the addresses from one OFDM symbol to another.
50. The method as claimed in claim 48, wherein the another operating mode is the 32k operating mode.
51. The method as claimed in claim 48, wherein the another operating mode is the operating mode having a predetermined maximum valid address of thirty two thousand seven hundred and sixty eight.
52. A data processing apparatus configured to map input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol, the data processing apparatus comprising:
an interleaver configured to read-into a memory a predetermined number of data symbols for mapping onto the OFDM sub-carrier signals, and to read-out of the memory the data symbols for the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on the sub-carrier signals, and an address generator configured to generate the set of addresses, the addresses indicating OFDM sub-carrier signals onto which of the data symbols are to be mapped, the address generator comprising: a linear feedback shift register including a predetermined number of register stages and being configured to generate a pseudo-random bit sequence in accordance with a generator polynomial, a permutation circuit configured to receive the content of the shift register stages and to permute the bits present in the register stages in accordance with a permutation order to form an address of one of the OFDM sub-carriers, and a control circuit configured in combination with an address check circuit to re-generate an address when a generated address exceeds a predetermined maximum valid address, wherein the predetermined maximum valid address is approximately sixteen thousand, the linear feedback shift register has thirteen register stages with a generator polynomial for the linear feedback shift register of R′ i [12]=R′ i −1[0]⊕ R′ i −1[1]⊕ R′ i −1[4]⊕ R′ i −1[5]⊕ R i −1[9]⊕ R′ i −1[11], and the permutation order forms, with an additional bit, a fourteen bit address R i [n] for the i-th data symbol from the bit present in the n-th register stage R′ i [n] and wherein the address generator comprises an offset generator configured to add an offset to the formed 14 bit address.
53. A data processing apparatus according to claim 52, wherein the linear feedback shift register is configured to generate the fourteen bit address in accordance with a code defined by the table:
R′ i bit positions
12
11
10
9
8
7
6
5
4
3
2
1
0
R i bit
8
4
3
2
0
11
1
5
12
10
6
7
9
positions.
54. A data processing apparatus as claimed in claim 52, wherein the offset generator is configured to add the offset to the formed fourteen bit address modulo the predetermined number of sub-carrier symbols.
55. A data processing apparatus as claimed in claim 52, wherein the offset generator generates the offset using another address generator.
56. A data processing apparatus as claimed in claim 55, wherein the predetermined number of sub-carrier signals is determined in accordance with one of a plurality of operating modes and the other address generator used by the offset generator to generate the offset is an address generator for one of the plurality of operating modes.
57. A data processing apparatus as claimed in claim 52, wherein the permutation circuit is arranged to change a permutation code, which permutes the order of the bits of the register stages to form the addresses from one OFDM symbol to another.
58. The data processing apparatus as claimed in claim 55, wherein the another address generator is an address generator configured to generate addresses having a predetermined maximum value of thirty two thousand seven hundred and sixty eight.
59. The data processing apparatus as claimed in claim 56, wherein the other address generator is the address generator for the 32k operating mode.
60. A transmitter for transmitting data using Orthogonal Frequency division Multiplexing (OFDM), the transmitter including data processing apparatus of claim 52.
61. A method of mapping input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol, the method comprising;
reading-into a memory a predetermined number of data symbols for mapping onto the OFDM sub-carrier signals, reading-out of the memory the data symbols for the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on the sub-carrier signals, and generating the set of addresses the addresses indicating sub-carrier signals onto which the data symbols are to be mapped, the generating the set of addresses comprising: using a linear feedback shift register including a predetermined number of register stages to generate a pseudo-random bit sequence in accordance with a generator polynomial, using a permutation circuit configured to receive the content of the shift register stages to permute the bits present in the register stages in accordance with a permutation order to form an address, and re-generating an address when a generated address exceeds a predetermined maximum valid address, wherein the predetermined maximum valid address is approximately sixteen thousand, the linear feedback shift register has thirteen register stages with a generator polynomial for the linear feedback shift register of R′ i [12]=R′ i −1[0]⊕ R′ i −1[1]⊕ R′ i −1[4]⊕ R′ i −1[5]⊕ R i −1[9]⊕ R′ i −1[11], and the permutation order forms, with an additional bit, a fourteen bit address R i [n] for the i-th data symbol from the bit present in the n-th register stage R′ i [n] and adding by offset generator circuitry an offset to the formed 14 bit address.
62. The method according to claim 61, wherein the linear feedback shift register generates the fourteen bit address in accordance with a code defined by the table:
R′ i bit positions
12
11
10
9
8
7
6
5
4
3
2
1
0
R i bit
8
4
3
2
0
11
1
5
12
10
6
7
9
positions.
63. The method as claimed in claim 61, wherein the adding the offset comprises adding the offset to the formed fourteen bit address modulo the predetermined number of sub-carrier symbols.
64. The method as claimed in claim 61, wherein the predetermined number of sub-carrier signals is determined in accordance with one of a plurality of operating modes and the adding the offset comprises generating an address for another of the plurality of operating modes.
65. The method as claimed in claim 64, comprising changing a permutation code, which permutes the order of the bits of the register stages to form the addresses from one OFDM symbol to another.
66. The method as claimed in claim 64, wherein the another operating mode is the 32k operating mode.
67. The method as claimed in claim 64, wherein the another operating mode is the operating mode having a predetermined maximum valid address of thirty two thousand seven hundred and sixty eight.Cited by (0)
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