Solid state imaging apparatus with a shared drain diffusion layer by adjacent cells

Abstract

While a drain power source of a reset transistor and a drain power source of an amplifying transistor are separated, the load of drain power source can be reduced by sharing a drain diffusion layer of the reset transistor and a drain diffusion layer of the amplifying transistor by adjacent cells in sharing pixel units. Further, an efficient pixel layout is provided by reducing the number of routing wires.

What is claimed is: 
     
       1. A solid state imaging apparatus, comprising:
 a cell in which K (K is an integer equal to 2 or greater) pixels are provided; 
 an amplifying transistor that is shared by the K pixels and amplifies signals read from the pixels; 
 a reset transistor that is shared by the K pixels and resets the signals read from the pixels; and 
 a row scanning circuit that drives a drain of the reset transistor separately between different rows while separating a drain power source of the reset transistor and the drain power source of the amplifying transistor, wherein 
 a drain diffusion layer of the reset transistor and the drain diffusion layer of the amplifying transistor are is shared by the different with the reset resistor of a first adjacent cells in a vertical direction cell, and a drain diffusion layer of the amplifying transistor is shared with the amplifying transistor of a second adjacent cell arranged in a vertical direction. 
 
     
     
       2. The solid state imaging apparatus according to  claim 1 , wherein the cell is provided with two pixels arranged in a vertical direction and the cells are arranged in such a way that a mirror image is formed with respect to the cells adjacent to each other in the vertical direction. 
     
     
       3. The solid state imaging apparatus according to  claim 2 , wherein the cell in an odd column has the amplifying transistor and the reset transistor shifted by two pixels with respect to the cell in an even column. 
     
     
       4. The solid state imaging apparatus according to  claim 1 , wherein the cell is provided with four pixels arranged in a vertical direction and the cells in an odd column are arranged point-symmetrically with respect the cells in an even column. 
     
     
       5. The solid state imaging apparatus according to  claim 4 , wherein the cell is provided with the four pixels arranged in the vertical direction, a drain diffusion layer of the reset transistor of a first cell in the odd column and the drain diffusion layer of the reset transistor of a second cell in the even column adjacent to each other in a horizontal direction are shared and the drain diffusion layer of the amplifying transistor of the first cell and the drain diffusion layer of the amplifying transistor of a third cell in the even column adjacent to the second cell in the vertical direction are shared. 
     
     
       6. The solid state imaging apparatus according to  claim 5 , wherein the first cell is shifted by two pixels in the vertical direction with respect to the second cell. 
     
     
       7. The solid state imaging apparatus according to  claim 1 , further comprising: a floating diffusion provided corresponding to the reset transistor. 
     
     
       8. The solid state imaging apparatus according to  claim 7 , further comprising:
 a photodiode that photoelectrically converts light from an object to be imaged in units of the pixels; and 
 a read transistor that reads a signal photoelectrically converted by the photodiode in units of the pixels. 
 
     
     
       9. The solid state imaging apparatus according to  claim 8 , wherein the photodiodes are arranged side by side and adjacent to each other in a column direction in the cell. 
     
     
       10. The solid state imaging apparatus according to  claim 1 , wherein a first cell, a second cell, and a third cell are successively arranged adjacent to each other in a same row, the amplifying transistor of the second cell is arranged adjacent to the amplifying transistor of the first cell, and the reset transistor of the second cell is arranged adjacent to the reset transistor of the third cell. 
     
     
       11. The solid state imaging apparatus according to  claim 1 , wherein the amplifying transistor of a first cell in an N (N is a positive integer)-th column and the amplifying transistor of a second cell in an (N+1)-th column are arranged in an M-th row and the reset transistor of the first cell in the N-th column and the reset transistor of the second cell in the (N+1)-th column are arranged in an (M+1)-th row. 
     
     
       12. The solid state imaging apparatus according to  claim 1 , wherein the amplifying transistor of a first cell in an N (N is a positive integer)-th column and the reset transistor of a second cell in an (N+1)-th column are arranged in an M-th row and the reset transistor of the first cell in the N-th column and the amplifying transistor of the second cell in the (N+1)-th column are arranged in an (M+1)-th row. 
     
     
       13. The solid state imaging apparatus according to  claim 1 , wherein a second cell is arranged adjacent to a first cell in a same row, a third cell is arranged adjacent to the second cell in the same row, the reset transistor of the first cell is arranged adjacent to the reset transistor of the second cell, and the amplifying transistor of the first cell is arranged adjacent to the amplifying transistor of the third cell. 
     
     
       14. The solid state imaging apparatus according to  claim 1 , wherein the amplifying transistor of a first cell in an N (N is a positive integer)-th column is arranged in an (M (M is a positive integer)+3)-th row, the reset transistor of the first cell in the N-th column is arranged in an (M+2)-th row, the amplifying transistor of a second cell in an (N+1)-th column is arranged in an M-th row, and the reset transistor of the second cell in the (N+1)-th column is arranged in an (M+1)-th row. 
     
     
       15. The solid state imaging apparatus according to  claim 1 , wherein the cell is provided with two pixels arranged in an M (M is a positive integer)-th row and an (M+1)-th row, the reset transistor of the cell in an N (N is a positive integer)-th column and the reset transistor of the cell in an (N+1)-th column are provided in the M-th row, and the amplifying transistor of the cell in the N-th column and the amplifying transistor of the cell in the (N+1)-th column are provided in the (M+1)-th row. 
     
     
       16. The solid state imaging apparatus according to  claim 1 , wherein the cell is provided with two pixels arranged in an M (M is a positive integer)-th row and an (M+1)-th row, the reset transistor of the cell in an N (N is a positive integer)-th column and the amplifying transistor of the cell in an (N+1)-th column are provided in the M-th row, and the amplifying transistor of the cell in the N-th column and the reset transistor of the cell in the (N+1)-th column are provided in the (M+1)-th row. 
     
     
       17. The solid state imaging apparatus according to  claim 1 , wherein the cell is provided with four pixels arranged in an M (M is a positive integer)-th row, an (M+1)-th row, an (M+2)-th row, and an (M+3)-th row, the reset transistor of a first cell in an N (N is a positive integer)-th column is provided in the (M+2)-th row, the amplifying transistor of the first cell in the N-th column is provided in the (M+3)-th row, the reset transistor of a second cell in the (N+1)-th column is provided in the (M+1)-th row, and the amplifying transistor of the second cell in the (N+1)-th column is provided in the M-th row. 
     
     
       18. The solid state imaging apparatus according to  claim 17 , wherein the reset transistor of the first cell is arranged between the pixel in the (M+2)-th row of the first cell and the pixel in the (M+2)-th row of the second cell, the amplifying transistor of the first cell is arranged between the pixel in the (M+3)-th row of the first cell and the pixel in the (M+3)-th row of the second cell, the reset transistor of the second cell is arranged between the pixel in the (M+1)-th row of the first cell and the pixel in the (M+1)-th row of the second cell, and the amplifying transistor of the second cell is arranged between the pixel in the M-th row of the first cell and the pixel in the M-th row of the second cell. 
     
     
       19. The solid state imaging apparatus according to  claim 17 , wherein a third cell arranged in the (N+1)-th row is provided adjacent to the second cell, the reset transistor of the first cell is arranged between the pixel in the (M+2)-th row of the first cell and the pixel in the (M+2)-th row of the third cell, the amplifying transistor of the first cell is arranged between the pixel in the (M+3)-th row of the first cell and the pixel in the (M+3)-th row of the third cell, the reset transistor of the second cell is arranged between the pixel in the (M+1)-th row of the first cell and the pixel in the (M+1)-th row of the second cell, and the amplifying transistor of the second cell is arranged between the pixel in the M-th row of the first cell and the pixel in the M-th row of the second cell. 
     
     
       20. A solid state imaging apparatus, comprising:
 a cell in which K (K is an integer equal to 2 or greater) pixels are provided;   an amplifying transistor that is shared by the K pixels and amplifies signals read from the pixels;   a reset transistor that is shared by the K pixels and resets the signals read from the pixels; and   a row scanning circuit that drives a drain of the reset transistor while separating a drain power source of the reset transistor and a drain power source of the amplifying transistor,   wherein a drain diffusion layer of the reset transistor is shared with the reset transistor of a first adjacent cell, and   wherein a drain diffusion layer of the amplifying transistor is shared with the amplifying transistor of a second adjacent cell arranged in a vertical direction.   
     
     
       21. The apparatus according to claim 20, wherein the drain diffusion layer of the reset transistor and the drain diffusion layer of the amplifying transistor are arranged in the vertical direction. 
     
     
       22. The apparatus according to claim 21, wherein the drain diffusion layer of the reset transistor, the drain diffusion layer of the amplifying transistor and a source diffusion layer of the amplifying transistor are arranged in the vertical direction. 
     
     
       23. The apparatus according to claim 20, wherein the amplifying transistor has a current path in the vertical direction. 
     
     
       24. The apparatus according to claim 20, wherein the K pixels of the second adjacent cell are arranged line-symmetrically to the K pixels of the cell. 
     
     
       25. The apparatus according to claim 20, wherein the K pixels are arranged in the vertical direction, and wherein the reset transistor and the amplifying transistor are arranged between the K pixels and the first adjacent cell. 
     
     
       26. The apparatus according to claim 25, wherein K equals 2. 
     
     
       27. The apparatus according to claim 20, wherein the K pixels are arranged in the vertical direction and wherein the reset transistor and the amplifying transistor are arranged in the vertical direction and adjacent to the K pixels in a horizontal direction. 
     
     
       28. The apparatus according to claim 20, wherein each of the K pixels is coupled to a read transistor. 
     
     
       29. The apparatus according to claim 20, further comprising a third adjacent cell arranged in a horizontal direction relative to the cell, the third adjacent cell has K (K is an integer equal to 2 or greater) pixels, wherein the K pixels of the third adjacent cell are adjacent to the cell. 
     
     
       30. The apparatus according to claim 20, wherein the cell has a first floating diffusion layer and a second floating diffusion layer, the first floating diffusion layer electrically connected to the second floating diffusion layer,
 wherein the K pixels have at least one first pixel and at least one second pixel,   wherein the first floating diffusion layer is connected to the at least one first pixel through a first read transistor, and   wherein the second floating diffusion layer is connected to the at least one second pixel through a second read transistor.   
     
     
       31. The apparatus according to claim 30, wherein the first floating diffusion layer and the second floating diffusion layer are commonly connected to the amplifying transistor and the reset transistor. 
     
     
       32. A solid state imaging apparatus, comprising:
 a first cell in which K (K is an integer equal to 2 or greater) pixels are provided;   an amplifying transistor that is shared by the K pixels and amplifies signals read from the pixels;   a reset transistor that is shared by the K pixels and resets the signals read from the pixels; and   a row scanning circuit that drives a drain of the reset transistor separately between different rows while separating a drain power source of the reset transistor and the drain power source of the amplifying transistor, wherein   a drain diffusion layer of the amplifying transistor is shared by the amplifying transistor of a second cell which is adjacent to and arranged in a vertical direction relative to the first cell,   a drain diffusion layer of the reset transistor is shared by the reset transistor of a third cell which is adjacent to and arranged in a horizontal direction relative to the first cell, and   a fourth cell is arranged adjacent to and in a horizontal direction relative to the first cell.   
     
     
       33. The apparatus according to claim 32 wherein the first cell is a cell in which K (K is an integer equal to 2 or greater) pixels are provided. 
     
     
       34. The apparatus according to claim 33 wherein the pixels of the first cell and the second cell are arranged vertically. 
     
     
       35. The apparatus according to claim 32 wherein the second cell is a cell in which K (K is an integer equal to 2 or greater) pixels are provided. 
     
     
       36. The apparatus according to claim 35 wherein the pixels of the first cell and the second cell are arranged vertically. 
     
     
       37. The apparatus according to claim 32 wherein the fourth cell is a cell in which K (K is an integer equal to 2 or greater) pixels are provided.