Cache pre-fetch architecture and method

Abstract

Embodiments of the present disclosure provide a system on a chip (SOC) comprising a processing core, and a cache including a cache instruction port, a cache data port, and a port utilization circuitry configured to selectively fetch instructions through the cache instruction port and selectively pre-fetch instructions through the cache data port. Other embodiments are also described and claimed.

What is claimed is: 
     
       1. A system on a chip (SOC) comprising:
 a processing core; and 
 a cache including:
 a cache instruction port; 
 a cache data port; and 
 
 a port utilization circuitry configured to:
 selectively fetch instructions through the cache instruction port; and 
 selectively pre-fetch instructions through only the cache data port; and 
 refrain from pre-fetching instructions through the cache instruction port. 
 
 
     
     
       2. The SOC of  claim 1 , wherein the port utilization circuitry is further configured to selectively fetch data through the cache data port and selectively pre-fetch data through the cache instruction port. 
     
     
       3. The SOC of  claim 1 , wherein the port utilization circuitry is configured to:
 issue a first request for fetching a first line of instruction, the first request transmitted through the cache instruction port; 
 determine that the cache data port is not currently being used to fetch data; and 
 issue, based on determining that the cache data port is not currently being used to fetch data, a second request for pre-fetching a second line of instruction, the second request transmitted through the cache data port. 
 
     
     
       4. The SOC of  claim 3 , wherein the port utilization circuitry is further configured to:
 issue a third request for fetching a first line of data, the third request transmitted through the cache data port; 
 determine that the cache instruction port is not currently being used to fetch instructions; and 
 issue, based on determining that the cache instruction port is not currently being used to fetch instructions, a fourth request for pre-fetching a second line of data, the fourth request transmitted through the cache instruction port. 
 
     
     
       5. The SOC of  claim 3 , further comprising a bridge module configured to:
 transmit the first request for fetching the first line of instruction from the cache instruction port to a memory; 
 receive, from the memory, the first line of instruction in response to transmitting the first request to the memory; and 
 transmit the received first line of instruction to the cache instruction port and the processing core. 
 
     
     
       6. The SOC of  claim 3 , further comprising a bridge module is configured to:
 transmit the second request for pre-fetching the second line of instruction from the cache data port to the a memory; 
 receive, from the memory, the second line of instruction in response to transmitting the second request to the memory; and 
 transmit the received second line of instruction only to the cache data port; and 
 refrain from transmitting the second line of instruction to the processing core. 
 
     
     
       7. The SOC of  claim 3 , further comprising a bridge module including a bridge instruction module and a bridge data module, wherein the bridge instruction module is operatively coupled to the cache instruction port and is configured to:
 transmit the first request for fetching the first line of instruction from the cache instruction port to a memory; 
 receive, from the memory, the first line of instruction in response to transmitting the first request to the memory; and 
 transmit the received first line of instruction to the cache instruction port and the processing core. 
 
     
     
       8. The SOC of  claim 7 , wherein the bridge data module is operatively coupled to the cache data port and is configured to:
 transmit the second request for pre-fetching the second line of instruction from the cache data port to the memory; 
 receive, from the memory, the second line of instruction in response to transmitting the second request to the memory; and 
 transmit the received second line of instruction only to the cache data port; and 
 refrain from transmitting the second line of instruction to the processing core. 
 
     
     
       9. The SOC of  claim 1 , wherein the port utilization circuitry comprises:
 a cache instruction logic module including an instruction read port and an instruction pre-fetch port; 
 a cache data logic module including a data read port and a data pre-fetch port; 
 a first multiplexer module configured to selectively connect the instruction read port and the data pre-fetch port to the cache instruction port; and 
 a second multiplexer module configured to selectively connect the data read port and the instruction fetch port to the cache data port. 
 
     
     
       10. The SOC of  claim 9 , wherein the cache instruction logic module is configured to:
 issue a first request for fetching a first line of instruction, the first request transmitted through the instruction read port, the first multiplexer, and the cache instruction port; 
 determine, in response to issuing the first request, that the cache data port is not currently being used by the cache data logic module; and 
 issue, based on determining that the cache data port is not currently being used by the cache data logic module, a second request for pre-fetching a second line of instruction, the second request transmitted through the instruction pre-fetch port, the second multiplexer, and the cache data port. 
 
     
     
       11. The SOC of  claim 10 , wherein the cache instruction logic module is configured to:
 issue the first request for fetching the first line of instruction based on receiving a request from the processing core for instructions included in the first line of instruction; 
 anticipate the processing core will request instructions included in the second line of instruction, based at least in part on receiving the said request for instructions from the processing core for instructions; and 
 issue the second request for pre-fetching the second line of instruction based at least in part on said anticipation. 
 
     
     
       12. The SOC of  claim 10 , wherein the cache data logic module is configured to:
 receive, from the processing core, a request for data from the processing core; 
 issue a third request for fetching a first line of data such that the data requested by the processing core is included in the first line of data, wherein the third request is transmitted through the data read port, the second multiplexer, and the cache data port; 
 determine that the cache instruction port is not currently being used by the cache instruction logic module; and 
 issue, based on determining that the cache instruction port is not currently being used by the cache instruction logic module, a fourth request for pre-fetching a second line of data, the fourth request transmitted through the data pre-fetch port, the first multiplexer, and the cache instruction port. 
 
     
     
       13. A method for operating a system on a chip (SOC) comprising a processing core and a cache, the cache including a cache instruction port and a cache data port, the method comprising:
 issuing a first request for fetching a first line of instruction through the cache instruction port; and 
 issuing a second request for pre-fetching a second line of instruction through only the cache data port; and 
 refraining from pre-fetching any line of instructions through the cache instruction port. 
 
     
     
       14. The method of  claim 13 , wherein issuing the second request further comprises:
 determining, in response to issuing the first request, that the cache data port is not currently being used by the cache; and 
 issuing the second request based on determining that the cache data port is not currently being used by the cache. 
 
     
     
       15. The method of  claim 13 , wherein the cache includes a cache instruction logic module, a cache data logic module, a first multiplexer and a second multiplexer, wherein the cache instruction logic module includes an instruction read port and an instruction pre-fetch port, and wherein the cache data logic module includes a data read port and a data pre-fetch port;
 wherein issuing the first request further comprises:
 issuing the first request, by the cache instruction logic module, through the instruction read port, the first multiplexer and the cache instruction port; and 
 
 wherein issuing the second request further comprises:
 issuing the second request, by the cache instruction logic module, through the instruction pre-fetch port, the second multiplexer and the cache data port. 
 
 
     
     
       16. The method of  claim 13 , further comprising:
 issuing a third request for fetching a first line of data through the cache data port; and 
 issuing a fourth request for pre-fetching a second line of data through the cache instruction port. 
 
     
     
       17. The method of  claim 13 , wherein SOC further includes a bridge module, the method further comprising:
 transmitting, by the bridge module, the first request for fetching the first line of instruction from the cache instruction port to a memory; 
 receiving, by the bridge module from the memory, the first line of instruction in response to transmitting the first request to the memory; and 
 
       transmitting the received first line of instruction to the cache instruction port and the processing core. 
     
     
       18. The method of  claim 13 , wherein SOC further includes a bridge module, the method further comprising:
 transmitting, by the bridge module, the second request for pre-fetching the second line of instruction from the cache data port to a memory; 
 receiving, by the bridge module from the memory, the second line of instruction in response to transmitting the second request to the memory; and 
 transmitting, by the bridge module, the received second line of instruction to the cache data port. 
 
     
     
       19. The method of  claim 18 , further comprising:
 refraining, by the bridge module, from transmitting the second line of instruction to the processing core.   
     
     
       20. The method of  claim 13 , further comprising:
 issuing the first request and the second request substantially simultaneously or in an over-lapping manner. 
 
     
     
       21. A system on a chip (SOC) comprising:
 a processing core;   a first wired communication link configured to selectively fetch data; and   a second wired communication link configured to (i) selectively fetch instructions, and (ii) selectively pre-fetch data while the second wired communication link is not fetching instructions, the second wired communication link being coupled to a cache instruction port, wherein the cache instruction port pre-fetches data through only the cache instruction port via the second wired communication link.   
     
     
       22. The SOC of claim 21, wherein the first wired communication link is further configured to selectively pre-fetch instructions while the first wired communication link is not fetching data. 
     
     
       23. The SOC of claim 21, further comprising:
 a cache comprising (i) a cache data port, the first wired communication link being coupled to the cache data port, and (ii) the cache instruction port.   
     
     
       24. The SOC of claim 23, wherein the cache further comprises:
 a port utilization circuitry configured to control the cache such that
 (A) the cache data port selectively fetches data via the first wired communication link, and 
 (B) the cache instruction port (i) selectively fetches instructions via the second wired communication link, and (ii) selectively pre-fetches data via the second wired communication link, while the second wired communication link is not selectively fetching instructions. 
   
     
     
       25. The SOC of claim 24, wherein the port utilization circuitry is further configured to control the cache such that (A) the cache data port selectively fetches data via the first wired communication link and (B) the cache instruction port selectively pre-fetches data via the second wired communication link. 
     
     
       26. The SOC of claim 24, wherein the port utilization circuitry is configured to:
 issue a first request for fetching a first line of instruction, the first request transmitted through the cache instruction port and the second wired communication link;   determine that the cache data port is not currently being used to fetch data; and   issue, based on determining that the cache data port is not currently being used to fetch data, a second request for pre-fetching a second line of instruction, the second request transmitted through the cache data port and the first wired communication link.   
     
     
       27. The SOC of claim 26, wherein the port utilization circuitry is further configured to:
 issue a third request for fetching a first line of data, the third request transmitted through the cache data port and the first wired communication link;   determine that the cache instruction port is not currently being used to fetch instructions; and   issue, based on determining that the cache instruction port is not currently being used to fetch instructions, a fourth request for pre-fetching a second line of data, the fourth request transmitted through the cache instruction port and the second wired communication link.   
     
     
       28. The SOC of claim 27, further comprising a bridge module configured to:
 transmit the first request for fetching the first line of instruction from the cache instruction port to a memory;   receive, from the memory, the first line of instruction in response to transmitting the first request to the memory; and   transmit the received first line of instruction to the cache instruction port and the processing core.   
     
     
       29. The SOC of claim 27, further comprising a bridge module configured to:
 transmit the second request for pre-fetching the second line of instruction from the cache data port to the memory;   receive, from the memory, the second line of instruction in response to transmitting the second request to the memory; and   transmit the received second line of instruction only to the cache data port.   
     
     
       30. The SOC of claim 27, further comprising a bridge module including a bridge instruction module and a bridge data module, wherein the bridge instruction module is operatively coupled to the cache instruction port, the bridge instruction module configured to:
 transmit the first request for fetching the first line of instruction from the cache instruction port to a memory;   receive, from the memory, the first line of instruction in response to transmitting the first request to the memory; and   transmit the received first line of instruction to the cache instruction port and to the processing core.   
     
     
       31. The SOC of claim 30, wherein the bridge data module is operatively coupled to the cache data port, the bridge data module configured to:
 transmit the second request for pre-fetching the second line of instruction from the cache data port to the memory;   receive, from the memory, the second line of instruction in response to transmitting the second request to the memory; and   transmit the received second line of instruction only to the cache data port.   
     
     
       32. The SOC of claim 24, wherein the port utilization circuitry comprises:
 a cache instruction logic module including an instruction read port and an instruction pre-fetch port;   a cache data logic module including a data read port and a data pre-fetch port;   a first multiplexer module configured to selectively connect the instruction read port and the data pre-fetch port to the cache instruction port; and   a second multiplexer module configured to selectively connect the data read port and the instruction fetch port to the cache data port.   
     
     
       33. The SOC of claim 32, wherein the cache instruction logic module is configured to:
 issue a first request for fetching a first line of instruction, the first request transmitted through the instruction read port, the first multiplexer, the cache instruction port, and the second wired communication link;   determine, in response to issuing the first request, that the cache data port is not currently being used by the cache data logic module; and   issue, based on determining that the cache data port is not currently being used by the cache data logic module, a second request for pre-fetching a second line of instruction, the second request transmitted through the instruction pre-fetch port, the second multiplexer, the cache data port, and the first wired communication link.   
     
     
       34. The SOC of claim 33, wherein the cache instruction logic module is configured to:
 issue the first request for fetching the first line of instruction based on receiving a request from the processing core for instructions included in the first line of instruction;   anticipate the processing core will request instructions included in the second line of instruction, based at least in part on receiving the request for instructions from the processing core; and   issue the second request for pre-fetching the second line of instruction based at least in part on said anticipation.   
     
     
       35. The SOC of claim 33, wherein the cache data logic module is configured to:
 receive a request for data from the processing core;   issue a third request for fetching a first line of data such that the data requested by the processing core is included in the first line of data, wherein the third request is transmitted through the data read port, the second multiplexer, the cache data port, and the first wired communication link;   determine that the cache instruction port is not currently being used by the cache instruction logic module; and   issue, based on determining that the cache instruction port is not currently being used by the cache instruction logic module, a fourth request for pre-fetching a second line of data, the fourth request transmitted through the data pre-fetch port, the first multiplexer, the cache instruction port, and the second wired communication link.   
     
     
       36. A method for operating a system on a chip (SOC) comprising a processing core, the method comprising:
 selectively fetching data via a first wired communication link;   selectively fetching instructions via a second wired communication link;   while instructions are not being fetched via the second wired communication link, selectively pre-fetching data via only the second wired communication link, the second wired communication link being coupled to a cache instruction port.   
     
     
       37. The method of claim 36, further comprising:
 while data are not being fetched via the first wired communication link, selectively pre-fetching instructions via the first wired communication link.   
     
     
       38. The method of claim 36, wherein the SOC comprises a cache, the cache including a cache instruction port and a cache data port, the method further comprising:
 issuing a first request for fetching a first line of instruction through the cache instruction port and the second wired communication link;   issuing a second request for pre-fetching a second line of instruction through only the cache data port and the first wired communication link.   
     
     
       39. The method of claim 38, wherein issuing the second request further comprises:
 determining, in response to issuing the first request, that the cache data port is not currently being used by the cache; and   issuing the second request based on determining that the cache data port is not currently being used by the cache.   
     
     
       40. The method of claim 38, wherein the cache includes a cache instruction logic module, a cache data logic module, a first multiplexer and a second multiplexer, wherein the cache instruction logic module includes an instruction read port and an instruction pre-fetch port, and wherein the cache data logic module includes a data read port and a data pre-fetch port;
 wherein issuing the first request further comprises:
 issuing the first request, by the cache instruction logic module, through the instruction read port, the first multiplexer, the cache instruction port, and the second wired communication link; and 
   wherein issuing the second request further comprises:
 issuing the second request, by the cache instruction logic module, through the instruction pre-fetch port, the second multiplexer, the cache data port, and the first wired communication link. 
   
     
     
       41. The method of claim 38, further comprising:
 issuing a third request for fetching a first line of data through the cache data port and the first wired communication link; and   issuing a fourth request for pre-fetching a second line of data through the cache instruction port and the second wired communication link.   
     
     
       42. The method of claim 38, wherein SOC further includes a bridge module, the method further comprising:
 transmitting, by the bridge module, the first request for fetching the first line of instruction from the cache instruction port to a memory;   receiving, by the bridge module from the memory, the first line of instruction in response to transmitting the first request to the memory; and   transmitting the received first line of instruction to the cache instruction port and the processing core.   
     
     
       43. The method of claim 38, wherein SOC further includes a bridge module, the method further comprising:
 transmitting, by the bridge module, the second request for pre-fetching the second line of instruction from the cache data port to a memory;   receiving, by the bridge module from the memory, the second line of instruction in response to transmitting the second request to the memory; and   transmitting, by the bridge module, the received second line of instruction to the cache data port.   
     
     
       44. The method of claim 38, further comprising:
 issuing the first request and the second request substantially simultaneously or in an over-lapping manner.