Integrated circuit device having pads structure formed thereon and method for forming the same

Abstract

The invention is to provide a structure of IC pad and its forming method. The structure is arranged in an insulation layer and is comprised of a lower electric-conduction layer, a compound layer structure and a pad layer. The lower electric-conduction layer is arranged at an appropriate position in the insulation layer and is connected to an electric potential. The compound layer structure is arranged on the insulation layer and is composed of at least one electric-conduction layer and at least one electric-conduction connecting layer, both are inter-overlapped to each other. The pad layer is arranged on the compound layer structure.

What is claimed is: 
     
       1. An integrated circuit (IC) device having a pad structure formed thereon, the IC device comprising:
 a) a substrate; 
 b) an insulation layer formed on the substrate; 
 c) a plurality of electric-conduction layers formed in the insulation layer, including a lower electric-conduction layer formed in the insulation layer, each electric-conduction layer having a thickness; 
 d) a plurality of connecting layers, each connecting layer having a thickness, the connecting layers interposed between the electric-conduction layers, the plurality of connecting layers selectively coupling one or more of the electric-conduction layers; 
 de) a compound layer structure formed in the insulation layer; 
 ef) a first pad layer formed on the insulation layer and coupled to the compound layer structure, wherein the first pad layer and the compound layer structure are spaced apart from the lower electric-conductionand substantially above from the lower electric-conduction layer, wherein the compound layer structure and the lower electric-conduction layer are spaced apart by the thickness of at least one electric-conduction layer and the thickness of at least one connecting layer, wherein the first pad layer is designated for signal transmission; and 
 fg) a second pad layer formed on the insulation layer and coupled to the lower electric-conduction layer, wherein the second pad layer is designated to be coupled to a power source; 
 h) at least one second connecting layer for coupling the second pad layer to the lower electric-conduction layer; and 
 i) at least one second electric-conduction layer coupled between the second pad layer and the lower electric-conduction layer with the second connecting layer. 
 
     
     
       2. The IC device according to  claim 1 , wherein the compound layer structure comprises a first electric-conduction layer and a first connecting layer to couple the first electric-conduction layer to the first pad layer. 
     
     
       3. The IC device according to  claim 2 , wherein the first connecting layer comprises a plurality of via plugs. 
     
     
       4. The IC device according to  claim 2 , wherein the first electric-conduction layer is shaped like a webbed railing. 
     
     
       5. The IC device according to  claim 2 , wherein the area of the first electric-conduction layer is smaller than that of the first pad layer. 
     
     
       6. The IC device according to  claim 1 , wherein the first pad layer is shaped like a polygon. 
     
     
       7. The IC device according to  claim 1 , further comprising a passivation layer formed on the insulation layer to cover a part of the outer rim of at least one of the first and second pad layers. 
     
     
       8. The IC device according to  claim 1 , further comprising at least one second connecting layer for coupling the second pad layer to the lower electric-conduction layer. 
     
     
       9. The IC device according to  claim 8 , further comprising at least one second electric-conduction layer coupled between the second pad layer and the lower electric-conduction layer with the second connecting layer. 
     
     
       10. The IC device according to  claim 1 , An integrated circuit (IC) device having a pad structure formed thereon, the IC device comprising:
 a) a substrate; 
 b) an insulation layer formed on the substrate; 
 c) a lower electric-conduction layer formed in the insulation layer; 
 d) a compound layer structure formed in the insulation layer; 
 e) a first pad layer formed on the insulation layer, substantially formed above the lower electric-conduction layer and coupled to the compound layer structure, wherein the first pad layer and the compound layer structure are spaced apart from the lower electric-conduction layer, wherein the first pad layer is designated for signal transmission; 
 f) a second pad layer formed on the insulation layer and coupled to the lower electric-conduction layer, wherein the second pad layer is designated to be coupled to a power source; 
 g) at least one second connecting layer for coupling the second pad layer to the lower electric-conduction layer; and 
 h) at least one second electric-conduction layer coupled between the second pad layer and the lower electric-conduction layer with the second connecting layer and disposed lower than the compound layer structure; 
 wherein a noise from the substrate is kept away from the first pad layer by the lower electric-conduction layer. 
 
     
     
       11. An integrated circuit (IC) device having a pad structure formed thereon, the IC device comprising:
 a) a substrate; 
 b) an insulation layer formed on the substrate; 
 c) a lower electric-conduction layer formed in the insulation layer; 
 d) a compound layer structure formed in the insulation layer; and 
 e) a first pad layer formed on the insulation layer and coupled to the compound layer structure, wherein the first pad layer and the compound layer structure are spaced apart from the lower electric-conduction layer, wherein the first pad layer is designated for signal transmission; 
 f) a second pad layer formed on the insulation layer and coupled to the lower electric-conduction layer, wherein the second pad layer is designated to be coupled to a power source; 
 g) at least one second connecting layer for coupling the second pad layer to the lower electric-conduction layer; and 
 h) at least one second electric-conduction layer coupled between the second pad layer and the lower electric-conduction layer with the second connecting layer and disposed lower than the compound layer structure. 
 
     
     
       12. The IC device according to  claim 11 , wherein the compound layer structure comprises a first electric-conduction layer and a first connecting layer to couple the first electric-conduction layer to the first pad layer. 
     
     
       13. The IC device according to  claim 11 , further comprising a second pad layer formed on the insulation layer and coupled to the lower electric-conduction layer. 
     
     
       14. The IC device according to  claim 13 , further comprising at least one second connecting layer for coupling the second pad layer to the lower electric-conduction layer; and at least one second electric-conduction layer coupled between the second pad layer and the lower electric-conduction layer with the second connecting layer. 
     
     
       15. The IC device according to claim  14  11, wherein, the area of the first electric-conduction layer is smaller than that of the first pad layer. 
     
     
       16. The IC device according to  claim 11 , wherein the first pad layer is shaped like a polygon. 
     
     
       17. The IC device according to  claim 11 , further comprising a passivation layer formed on the insulation layer to cover a part of the outer rim of at least one of the first and second pad layers. 
     
     
       18. The IC device according to  claim 11 , wherein a noise from the substrate is kept away from the first pad layer by the lower electric-conduction layer. 
     
     
       19. A method for fabricating an IC device having a pad structure formed thereon, the method comprising:
 a) providing a substrate; 
 b) forming an insulation layer formed on the substrate; 
 c) forming a lower electric-conduction layer formed in the insulation layer, at least a part of the lower electric-conduction layer being covered by the insulation layer; 
 d) forming a compound layer structure formed in the insulation layer, the compound layer structure being spaced apart from and not connected to the lower electric-conduction layer; and 
 e) forming a first pad layer formed on the insulation layer, the first pad layer being coupled to the compound layer, 
 wherein in the forming a first pad layer step e) the first pad layer and the compound layer are spaced apart from the lower electric-conduction layer; 
 f) forming a second pad layer formed on the insulation layer and coupled to the lower electric-conduction layer, wherein the second pad layer is designated to be coupled to a power source; 
 g) forming at least one second connecting layer for coupling the second pad layer to the lower electric-conduction layer; and 
 h) forming at least one second electric-conduction layer coupled between the second pad layer and the lower electric-conduction layer with the second connecting layer. 
 
     
     
       20. The method according to  claim 19 , wherein a noise from the substrate is kept away form from the first pad layer by the lower electric-conduction layer. 
     
     
       21. The method according to  claim 19 , wherein the forming a compound layer structure step d) further comprises the steps of:
 forming at least one first electric-conduction layer on the insulation layer; and 
 forming at least one first connecting layer on the insulation layer, wherein the first connecting layer is to couple the first electric-conduction layer to the first pad layer. 
 
     
     
       22. The method according to  claim 21 , wherein the area of the first electric-conduction layer is smaller than that of the first pad layer. 
     
     
       23. The IC device according to claim 1, wherein the lower electric-conduction layer is lowest in depth of the plurality of electric-conduction layers. 
     
     
       24. The IC device according to claim 1, wherein the at least one electric-conduction layer is not substantially disposed between the first pad layer and an area of the lower electric-conduction layer beneath the first pad layer. 
     
     
       25. The IC device according to claim 1, wherein the lower electric-conduction layer is disposed such that an area of the first pad layer substantially intersects the lower electric-conduction layer when superimposed on the lower electric-conduction layer. 
     
     
       26. The IC device according to claim 25, wherein the lower electric-conduction layer is comprised of a plurality of sub-layers disposed at the same depth. 
     
     
       27. The IC device according to claim 1, wherein the second pad layer is designated to be coupled to a ground potential. 
     
     
       28. The IC device according to claim 1, wherein the second pad layer is designated to be coupled to a voltage potential. 
     
     
       29. The IC device according to claim 1, wherein the first pad layer is designated to be coupled to a high frequency signal. 
     
     
       30. The IC device according to claim 10, wherein the compound layer structure comprises a first electric-conduction layer and a first electric-conduction connecting layer for coupling the first electric-conduction layer to the first pad layer. 
     
     
       31. The IC device according to claim 30, further comprising:
 a second electric-conduction layer, comprised of a first and second sub-layers at the same depth,   a second electric-conduction connecting layer, comprised of first and second sub-layers at the same depth,   wherein the first sub-layer of the second electric-conduction layer and the first sub-layer of the second electric-conduction connecting layer couple the second pad layer with a first portion of the lower electric-conduction layer.   
     
     
       32. The IC device according to claim 31, further comprising:
 a third electric-conduction layer, comprised of a first and second sub-layers at the same depth,   a third electric-conduction connecting layer, comprised of a first and second sub-layers at the same depth;   wherein the second sub-layer of the third electric-conduction layer and the second sub-layer of the third electric-conduction connecting layer couple a third pad layer with a second portion of the lower electric-conduction layer.   
     
     
       33. The IC device according to claim 31, wherein the second pad layer is designated to be coupled to a ground potential. 
     
     
       34. The IC device according to claim 31, wherein the second pad layer is designated to be coupled to a voltage potential. 
     
     
       35. The IC device according to claim 31, wherein the first pad layer is designated to be coupled to a high frequency signal. 
     
     
       36. The IC device according to claim 29, wherein the compound layer structure and the lower electric-conduction layer are spaced apart by at least one electric-conduction layer and at least one connecting layer. 
     
     
       37. The IC device according to claim 36, further comprising multiple second electric-conduction layers, multiple second electric-conduction connecting layers, multiple third electric-conduction layers, multiple third electric-conduction connecting layers; wherein the multiple second electric-conduction layers and the multiple second electric-conduction connecting layers are used to couple the second pad layer with one side of the lower electric-conduction layer, and the multiple third electric-conduction layers and the multiple third electric-conduction connecting layers are used to couple the other second pad layer with the other side of the lower electric-conduction layer. 
     
     
       38. The IC device according to claim 37, wherein the multiple second electric-conduction layers, multiple second electric-conduction connecting layers, multiple third electric-conduction layers, multiple third electric-conduction connecting layers and the lower electric-conduction layer are formed as a U-shaped structure. 
     
     
       39. The IC device according to claim 38, further comprising a passivation layer formed on the insulation layer, wherein the bonding zone of the passivation layer is smaller than the area of first and second pad layers. 
     
     
       40. The IC device according to claim 39, wherein the second pad layer and the other second pad layer are coupled to a power source. 
     
     
       41. The IC device according to claim 10, wherein the noise from the substrate is generated by an integrated circuit. 
     
     
       42. The IC device according to claim 10, further comprising multiple second electric-conduction layers, multiple second electric-conduction connecting layers, multiple third electric-conduction layers, multiple third electric-conduction connecting layers; wherein the multiple second electric-conduction layers and the multiple second electric-conduction connecting layers are used to couple the second pad layer with one side of the lower electric-conduction layer, and the multiple third electric-conduction layers and the multiple third electric-conduction connecting layers are used to couple the other second pad layer with the other side of the lower electric-conduction layer. 
     
     
       43. The IC device according to claim 42, wherein the multiple second electric-conduction layers, multiple second electric-conduction connecting layers, multiple third electric-conduction layers, multiple third electric-conduction connecting layers and the lower electric-conduction layer are formed as a U-shaped structure. 
     
     
       44. The IC device according to claim 10, wherein first pad layer is designated to be coupled to a high frequency signal and the second pad layer is designated to be coupled to a voltage potential or ground potential.