Semiconductor memory device with variable resistance element

Abstract

According to one embodiment, a semiconductor memory device includes a variable resistance element configured to store data “0” and data “1” in accordance with a change in resistance value, a current generator configured to generate a reference current for determining data of the variable resistance element, and having an admittance middle at a level in between an admittance of a variable resistance element storing data “0” and an admittance of a variable resistance element storing data “1”, and a sense amplifier includes a first input terminal connected to the variable resistance element and a second input terminal connected to the current generator, and configured to compare currents of the first input terminal and the second input terminal.

What is claimed is: 
     
       1. A semiconductor memory device comprising:
 a variable resistance element configured to store a first data and a second data in accordance with a change in resistance value; 
 a current generator configured to generate a reference current for determining data of the variable resistance element, and having a middle admittance between an admittance of the variable resistance element storing the first data and an admittance of the variable resistance element storing the second data; and 
 a sense amplifier comprising a first input terminal connected to the variable resistance element and a second input terminal connected to the current generator, and configured to compare currents of the first input terminal and the second input terminal, 
 wherein the middle admittance Ymid satisfies the following equation
   Ymid =(Rmax +Rmin)/(2Rmax*Rmin) 
 
 where Rmin is a resistance value of the variable resistance element storing the first data, and Rmax is a resistance value of the variable resistance element storing the second data. 
 
     
     
       2. The device of  claim 1 , wherein the current generator comprises resistance elements having the same structure as a structure of the variable resistance element. 
     
     
       3. The device of  claim 1 , wherein the current generator comprises:
 a first bit line, a second bit line, and a third bit line; 
 a first current path comprising a first resistance element connected between the first bit line and the second bit line, and a second resistance element connected between the second bit line and the third bit line; and 
 a second current path comprising a third resistance element connected between the first bit line and the second bit line, and a fourth resistance element connected between the second bit line and the third bit line, 
 the first resistance element and the second resistance element have the same resistance value as a resistance value of the variable resistance element storing the first data, and 
 the third resistance element and the fourth resistance element have the same resistance value as a resistance value of the variable resistance element storing the second data. 
 
     
     
       4. The device of  claim 3 , wherein
 the first bit line is connected to the second input terminal of the sense amplifier, and 
 the third bit line is grounded. 
 
     
     
       5. The device of  claim 3 , wherein a variable resistance element as a memory element is connected between the first bit line and the second bit line. 
     
     
       6. The device of  claim 3 , wherein
 the first resistance element and the second resistance element are configured to supply a current in a direction to write the first data in a read operation, and 
 the third resistance element and the fourth resistance element are configured to supply a current in a direction to write the second data in the read operation. 
 
     
     
       7. The device of  claim 3 , further comprising:
 a first selection transistor connected to a first terminal of the first resistance element; 
 a second selection transistor connected to a first terminal of the second resistance element; 
 a third selection transistor connected to a first terminal of the third resistance element; 
 a fourth selection transistor connected to a first terminal of the fourth resistance element; 
 a first dummy word line connected to a gate of the first selection transistor; 
 a second dummy word line connected to a gate of the second selection transistor; 
 a third dummy word line connected to a gate of the third selection transistor; and 
 a fourth dummy word line connected to a gate of the fourth selection transistor. 
 
     
     
       8. The device of  claim 7 , further comprising a row decoder configured to control the first dummy word line, the second dummy word line, the third dummy word line, and the fourth dummy word line. 
     
     
       9. The device of  claim 3 , further comprising:
 first and second selection transistors connected to a first terminal of the first resistance element; 
 third and fourth selection transistors connected to a first terminal of the second resistance element; 
 fifth and sixth selection transistors connected to a first terminal of the third resistance element; 
 seventh and eighth selection transistors connected to a first terminal of the fourth resistance element; 
 first and second dummy word lines connected to gates of the first and second selection transistors, respectively; 
 third and fourth dummy word lines connected to gates of the third and fourth selection transistors, respectively; 
 fifth and sixth dummy word lines connected to gates of the fifth and sixth selection transistors, respectively; and 
 seventh and eighth dummy word lines connected to gates of the seventh and eighth selection transistors, respectively. 
 
     
     
       10. The device of  claim 9 , further comprising a row decoder configured to control the first to eighth dummy word lines. 
     
     
       11. The device of  claim 1 , further comprising:
 a selection transistor connected to a first terminal of the variable resistance element; and 
 a word line connected to a gate of the selection transistor. 
 
     
     
       12. The device of  claim 1 , further comprising:
 first and second selection transistors connected to a first terminal of the variable resistance element; and 
 first and second word lines connected to gates of the first and second selection transistors, respectively. 
 
     
     
       13. The device of  claim 1 , wherein the variable resistance element comprises a fixed layer comprising a fixed magnetization direction, a recording layer comprising a variable magnetization direction, and a nonmagnetic layer between the fixed layer and the recording layer. 
     
     
       14. A semiconductor memory device, comprising:
 a first memory array including a first memory unit comprising a plurality of memory cells and including variable resistance elements configurable to have one of a first resistive state and a second resistive state, a variable resistance element in each memory cell being connected between a first bit line and a second bit line;   a second memory array including a second memory unit comprising a plurality of memory cells and including variable resistance elements configurable to have one of the first resistive state and the second resistive state, a variable resistance element in each memory cell being connected between a third bit line and a fourth bit line; and   a sense amplifier connected between the first and second memory arrays and configured to read data from the second memory array using a reference current supplied from the first memory array, wherein   the first memory array includes first through fourth dummy memory cells which each include a variable resistance element configurable to have one of the first resistive state and the second resistive state,   the first dummy memory cell has a variable resistance element that is configurable to have the first resistive state and is connected between the first bit line and a fifth bit line having a fixed potential,   the second dummy memory cell has a variable resistance element that is configurable to have the second resistive state and is connected between the first bit line and the fifth bit line,   the third dummy memory cell has a variable resistance element that is configurable to have the second resistive state and is connected between the first bit line and the second bit line,   the fourth dummy memory cell has a variable resistance element that is configurable to have the first resistive state and is connected between the first bit line and the second bit line and to the fifth bit line through the first and second dummy memory cells; and   a middle admittance of the first memory array is equal to the sum of a first resistance value for a variable resistance element in the first resistive state and a second resistance value for a variable resistance element in the second resistive state divided by the product of twice the first resistance value and the second resistance value, wherein   the first resistance value is a resistance value of a variable resistance element storing first data, and the second resistance value is a resistance value of a variable resistance element storing second data.   
     
     
       15. The semiconductor memory device according to claim 14, wherein the reference current is between a read current of a memory cell having a variable resistance element with the first resistive state and a read current of a memory cell having a variable resistance element with the second resistive state. 
     
     
       16. The semiconductor memory device according to claim 15, wherein each variable resistance element is a magnetic tunnel junction element. 
     
     
       17. The semiconductor memory device according to claim 15, wherein each variable resistance element includes a phase-change material. 
     
     
       18. The semiconductor memory device according to claim 15, wherein each variable resistance element includes a recording layer made of a perovskite metal oxide or a transition metal oxide. 
     
     
       19. A reference current generator in a semiconductor memory device, comprising:
 a first variable resistance element in a first dummy memory cell of a first memory unit and connected between a first terminal and a first node;   a second variable resistance element in a second dummy memory cell of the first memory unit and connected between the first terminal and the first node;   a third variable resistance element in a third dummy memory cell of the first memory unit and connected between the first node and a second terminal; and   a fourth variable resistance element in a fourth dummy memory cell of the first memory unit and connected between the first node and the second terminal, wherein   the first variable resistance element is configurable to have a first resistive state,   the second variable resistance element is configurable to have a second resistive state that is less than the first resistive state,   the third variable resistance element is configurable to have the first resistive state,   the fourth variable resistance element is configurable to have the second resistive state, and   a middle admittance of the reference current generator is equal to the sum of a first resistance value of the first or the third variable resistance element in the first resistive state and a second resistance value of the second or the fourth variable resistance element in the second resistive state divided by the product of twice the first resistance value and the second resistance value, wherein   the first resistance value corresponds to storage of first data, and the second resistance value corresponds to storage of second data.   
     
     
       20. The reference current generator according to claim 19, wherein each variable resistance element is a magnetic tunnel junction element. 
     
     
       21. The reference current generator according to claim 19, wherein each variable resistance element includes a phase-change material. 
     
     
       22. The reference current generator according to claim 19, wherein each variable resistance element includes a recording layer made of a perovskite metal oxide or a transition metal oxide. 
     
     
       23. The reference current generator according to claim 19, wherein a reference current supplied by the reference current generator is between a read current of a memory cell having a variable resistance element with the first resistive state and a read current of a memory cell having a variable resistance element with the second resistive state. 
     
     
       24. The semiconductor memory device according to claim 14, wherein the sense amplifier is physically disposed between the first memory array and the second memory array. 
     
     
       25. The semiconductor memory device according to claim 24, wherein each variable resistance element is a magnetic tunnel junction element. 
     
     
       26. The semiconductor memory device according to claim 24, wherein each variable resistance element includes a phase-change material. 
     
     
       27. The semiconductor memory device according to claim 24, wherein each variable resistance element includes a recording layer made of a perovskite metal oxide or a transition metal oxide.