Nonvolatile semiconductor memory device

Abstract

A nonvolatile semiconductor memory device includes: a memory unit; and a control unit. The memory unit includes: a multilayer structure including electrode films and interelectrode insulating films alternately stacked; a semiconductor pillar piercing the multilayer structure; insulating films and a memory layer provided between the electrode films and the semiconductor pillar; and a wiring connected to the semiconductor pillar. In an erase operation, the control unit performs: a first operation setting the wiring at a first potential and the electrode film at a second potential lower than the first potential during a first period; and a second operation setting the wiring at a third potential and the electrode film at a fourth potential lower than the third potential during a second period after the first operation. A length of the second period is shorter than the first period, and/or a difference between the third and fourth potentials is smaller than a difference between the first and second potentials.

The invention claimed is: 
     
       1. A nonvolatile semiconductor memory device comprising:
 a memory unit; and 
 a control unit, 
 the memory unit including:
 a multilayer structure including a plurality of electrode films and a plurality of interelectrode insulating films alternately stacked in a first direction; 
 a first semiconductor pillar piercing the multilayer structure in the first direction; 
 a first memory layer provided between each of the electrode films and the first semiconductor pillar; 
 a first inner insulating film provided between the first memory layer and the first semiconductor pillar; 
 a first outer insulating film provided between each of the electrode films and the first memory layer; and 
 a first wiring electrically connected to one end of the first semiconductor pillar, 
 
 the control unit performing:
 a first operation setting the first wiring at a first potential and setting the electrode film at a second potential lower than the first potential during a first period; and 
 an operation including a second operation setting the first wiring at a third potential and setting the electrode film at a fourth potential lower than the third potential during a second period after the first operation, 
 the operation including the second operation having at least one of: 
 a length of the second period being shorter than a length of the first period; and 
 a difference between the third potential and the fourth potential being smaller than a difference between the first potential and the second potential, 
 the first operation and the operation including the second operation being performed in an operation for performing at least one of injection of holes into the first memory layer and extraction of electrons from the first memory layer. 
 
 
     
     
       2. The device according to  claim 1 , wherein the control unit performs a third operation reading a threshold voltage of a memory transistor formed at an intersection between the first semiconductor pillar and the electrode film at least one of after the second operation and between the first operation and the second operation. 
     
     
       3. The device according to  claim 2 , wherein
 the third operation is performed after the second operation, 
 the control unit performs an operation setting the first wiring at an eighth potential and setting the electrode film at a ninth potential lower than the eighth potential during a third period after the third operation, and 
 the operation preformed during the third period includes at least one of: a length of the third period being shorter than the length of the second period; and a difference between the eighth potential and the ninth potential being smaller than the difference between the third potential and the fourth potential. 
 
     
     
       4. The device according to  claim 1 , wherein
 the memory unit further includes a select gate stacked on the multilayer structure in the first direction and pierced by the one end of the semiconductor pillar, and 
 the control unit sets:
 the select gate at a fifth potential during the first period, the fifth potential being lower than the first potential and higher than the second potential; and 
 the select gate at a sixth potential during the second period, the sixth potential being lower than the third potential and higher than the fourth potential. 
 
 
     
     
       5. The device according to  claim 4 , wherein a difference between the fifth potential and the second potential and a difference between the sixth potential and the second potential are lower than a breakdown voltage of a select gate transistor of the select gate. 
     
     
       6. The device according to  claim 4 , wherein
 a potential of the select gate starts changing from the second potential to the fifth potential after a time when a potential of the first wiring starts changing from the second potential to the first potential during the first period, and 
 the potential of the select gate finishes changing from the fifth potential to the second potential after the time when the potential of the first wiring finishes changing from the first potential to the second potential during the second period. 
 
     
     
       7. The device according to  claim 4 , wherein
 the control unit performs a third operation reading a threshold voltage of a memory transistor formed at an intersection between the first semiconductor pillar and the electrode film at least one of after the second operation and between the first operation and the second operation, and 
 the control unit sets the first wiring at the second potential, sets the select gate at a potential being lower than the first potential and higher than the second potential, and reads the threshold voltage of the memory transistor with the potential of the electrode film varied between the first potential and the second potential in the third operation. 
 
     
     
       8. The device according to  claim 1 , wherein
 the memory unit further includes:
 a second semiconductor pillar provided adjacent to the first semiconductor pillar in a second direction orthogonal to the first direction and piercing the multilayer structure in the first direction; 
 a second memory layer provided between each of the electrode films and the second semiconductor pillar; 
 a second inner insulating film provided between the second memory layer and the second semiconductor pillar; 
 a second outer insulating film provided between each of the electrode films and the second memory layer; 
 a second wiring electrically connected to one end of the second semiconductor pillar; and 
 a connecting portion electrically connecting between another end opposite to the one end of the first semiconductor pillar and another end opposite to the one end of the second semiconductor pillar, 
 
 the control unit sets:
 the second wiring in a floating state during the first period of the first operation; and 
 the second wiring in the floating state during the second period of the second operation. 
 
 
     
     
       9. The device according to  claim 1 , wherein
 the memory unit further includes:
 a second semiconductor pillar provided adjacent to the first semiconductor pillar in a second direction orthogonal to the first direction and piercing the multilayer structure in the first direction; 
 a second memory layer provided between each of the electrode films and the second semiconductor pillar; 
 a second inner insulating film provided between the second memory layer and the second semiconductor pillar; 
 a second outer insulating film provided between each of the electrode films and the second memory layer; 
 a second wiring electrically connected to one end of the second semiconductor pillar; 
 a connecting portion electrically connecting between another end opposite to the one end of the first semiconductor pillar and another end opposite to the one end of the second semiconductor pillar; 
 a first select gate provided between the one end of the first semiconductor pillar and the multilayer structure and pierced by the first semiconductor pillar; and 
 a second select gate provided between the one end of the second semiconductor pillar and the multilayer structure and pierced by the second semiconductor pillar, 
 
 the control unit sets:
 the second wiring in a floating state; 
 the first select gate at a fifth potential being lower than the first potential and higher than the second potential; and 
 the second select gate at the fifth potential or in the floating state, during the first period of the first operation, and 
 
 the control unit sets:
 the second wiring in the floating state; 
 the first select gate at a sixth potential being lower than the third potential and higher than the fourth potential; and 
 the second select gate at the sixth potential or in the floating state, during the second period of the second operation. 
 
 
     
     
       10. The device according to  claim 9 , wherein a difference between the fifth potential and the second potential is lower than a breakdown voltage of a select gate transistor of the first select gate. 
     
     
       11. The device according to  claim 10 , wherein a difference between the sixth potential and the second potential is lower than the breakdown voltage of a select gate transistor of the second select gate. 
     
     
       12. The device according to  claim 9 , wherein the control unit performs a third operation reading a threshold voltage of a memory transistor formed at an intersection between the first semiconductor pillar and the electrode film at least one of after the second operation and between the first operation and the second operation. 
     
     
       13. The device according to  claim 12 , wherein
 the control unit sets the first wiring at the second potential, sets the second wiring, the first select gate, and the second select gate at a potential being lower than the first potential and higher than the second potential, and reads the threshold voltage of the memory transistor with the potential of the electrode film varied between the first potential and the second potential, in the third operation. 
 
     
     
       14. The device according to  claim 1 , wherein the memory layer includes a monolayer film made of a material selected from a first group including silicon nitride, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnia, hafnium aluminate, hafnia nitride, hafnium nitride aluminate, hafnium silicate, hafnium nitride silicate, lanthanum oxide, and lanthanum aluminate, or a multilayer film made of a plurality of materials selected from the first group. 
     
     
       15. The device according to  claim 14 , wherein at least one of the interelectrode insulating film, the inner insulating film, and the outer insulating film includes a monolayer film made of a material selected from a second group including silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnia, hafnium aluminate, hafnia nitride, hafnium nitride aluminate, hafnium silicate, hafnium nitride silicate, lanthanum oxide, and lanthanum aluminate, or a multilayer film made of a plurality of materials selected from the second group. 
     
     
       16. A nonvolatile semiconductor memory device comprising:
 a memory unit; and 
 a control unit, 
 the memory unit including:
 a multilayer structure including a plurality of electrode films and a plurality of interelectrode insulating films alternately stacked in a first direction; 
 a semiconductor pillar piercing the multilayer structure in the first direction; 
 a memory layer provided between each of the electrode films and the semiconductor pillar; 
 an inner insulating film provided between the memory layer and the semiconductor pillar; 
 an outer insulating film provided between each of the electrode films and the memory layer; and 
 a wiring electrically connected to one end of the semiconductor pillar, and 
 
 the control unit setting:
 the wiring at a first potential; and 
 the electrode film opposed to one of memory sections of the memory layer facing the plurality of electrode films at a second potential lower than the first potential and the electrode film opposed to the memory section except the one of memory sections in a floating state, 
 the setting being performed in an operation for performing at least one of injection of holes into the one memory section and extraction of electrons from the one memory section. 
 
 
     
     
       17. The device according to  claim 16 , wherein
 the one memory section is a first selected memory section, 
 the control unit sets:
 the wiring at the first potential, the electrode film opposed to the first selected memory section at the second potential lower than the first potential, and the electrode film opposed to the memory sections except the first selected memory section in the floating state during a first period in the operation for performing at least one of injection of holes into the first selected memory section and extraction of electrons from the first selected memory section; and 
 the wiring at a third potential, the electrode film opposed to a second selected memory section at a fourth potential lower than the third potential, and the electrode film opposed to the memory section except the second selected memory section in the floating state during a second period after the first period in an operation for performing at least one of injection of holes into the second selected memory section of the plurality of memory sections other than the first selected memory section and extraction of electrons from the second selected memory section, 
 
 the operation performed during the second period including at least one of:
 a length of the second period being different from a length of the first period; and 
 a difference between the third potential and the fourth potential being different from a difference between the first potential and the second potential. 
 
 
     
     
       18. The device according to  claim 17 , wherein
 the memory unit further includes:
 a second semiconductor pillar provided adjacent to the first semiconductor pillar in a second direction orthogonal to the first direction and piercing the multilayer structure in the first direction; 
 a second memory layer provided between each of the electrode films and the second semiconductor pillar; 
 a second inner insulating film provided between the second memory layer and the second semiconductor pillar; 
 a second outer insulating film provided between each of the electrode films and the second memory layer; 
 a second wiring electrically connected to one end of the second semiconductor pillar; 
 a connecting portion electrically connecting between another end opposite to the one end of the first semiconductor pillar and another end opposite to the one end of the second semiconductor pillar; 
 a first select gate provided between the one end of the first semiconductor pillar and the multilayer structure and pierced by the first semiconductor pillar; and 
 a second select gate provided between the one end of the second semiconductor pillar and the multilayer structure and pierced by the second semiconductor pillar, 
 
 the control unit setting:
 the second wiring in a floating state; 
 the first select gate at a fifth potential being lower than the first potential and higher than the second potential; and 
 the second select gate at the fifth potential or in the floating state, during the first period of the operation, and 
 
 the control unit setting:
 the second wiring in the floating state; 
 the first select gate at a sixth potential being lower than the third potential and higher than the fourth potential; and 
 the second select gate at the sixth potential or in the floating state, during the second period of the operation. 
 
 
     
     
       19. A nonvolatile semiconductor memory device comprising:
 a memory unit; and 
 a control unit, 
 the memory unit including:
 a multilayer structure including a plurality of electrode films and a plurality of interelectrode insulating films alternately stacked in a first direction; 
 a semiconductor pillar piercing the multilayer structure in the first direction; 
 a memory layer provided between each of the electrode films and the semiconductor pillar; 
 an inner insulating film provided between the memory layer and the semiconductor pillar; 
 an outer insulating film provided between each of the electrode films and the memory layer; and 
 a wiring electrically connected to one end of the semiconductor pillar, and 
 
 the control unit setting:
 the wiring at a first potential 
 one electrode film of the plurality of electrode films at a second potential lower than the first potential; and 
 another electrode film of the plurality of electrode films at a seventh potential lower than the first potential and different from the second potential, 
 
 the setting being performed in an operation for performing at least one of injection of holes into the memory layer and extraction of electrons from the memory layer. 
 
     
     
       20. The device according to  claim 19 , wherein
 the memory unit includes a first region and a second region, an outer diameter of the outer insulating film along a second direction perpendicular to the first direction in the first region is larger than an outer diameter of the outer insulating film along the second direction in the second region, 
 the one electrode film of the plurality of electrode films is an electrode film in the first region, and the another electrode film of the plurality of electrode films is an electrode film in the second region, and 
 the seventh potential is higher than the second potential. 
 
     
     
       21. A nonvolatile semiconductor memory device comprising:
 a block including a first memory string and a second memory string, the first memory string including a first memory cell and a second memory cell being connected to the first memory cell in series, the second memory cell being disposed above the first memory cell, the second memory string including a third memory cell and a fourth memory cell being connected to the third memory cell in series, the third memory cell being disposed above the fourth memory cell;   a first word line connected to the first memory cell;   a second word line connected to the second memory cell;   a third word line connected to the third memory cell;   a fourth word line connected to the fourth memory cell; and   a control circuit that applies a first voltage to the first word line and the third word line in an erase operation and to apply a second voltage to the second word line and the fourth word line in the erase operation, the first voltage being different from the second voltage, the erase operation being performed for the first memory cell, the second memory cell, the third memory cell, and the fourth memory cell.   
     
     
       22. The device according to claim 21, further comprising:
 a first wiring connected to one end of the first memory string,   wherein the control circuit applies a third voltage to the first wiring.   
     
     
       23. The device according to claim 22, further comprising:
 a semiconductor substrate;   a first silicon material, the first silicon material being included in the first memory string and extending in a first direction crossing to the semiconductor substrate; and   a first select gate transistor having a first gate electrode, and one end of the first select gate transistor connecting to the first silicon material and the other end of the first select gate transistor connecting to the first wiring,   wherein, in the erase operation, the control circuit applies a fourth voltage different from the third voltage to the first gate electrode.   
     
     
       24. The device according to claim 21, further comprising:
 a fifth word line connected to a first memory cell, the fifth word line included in the first memory string, and the fifth word line disposed above the second word line,   wherein, in the erase operation, the control circuit applies a fifth voltage to the fifth word line, the fifth voltage being different from the first voltage and the second voltage.   
     
     
       25. The device according to claim 24, wherein the second voltage is between the first voltage and the fifth voltage. 
     
     
       26. The device according to claim 21, further comprising:
 a fifth word line disposed above the second word line,   wherein the control circuit applies the second voltage to the fifth word line in the erase operation.   
     
     
       27. The device according to claim 23, wherein a width of a part of the first silicon material at the position which the first word line is disposed is narrower than a width of a part of the first silicon material at the position which the second word line is disposed. 
     
     
       28. The device according to claim 27, wherein the first voltage is higher than the second voltage. 
     
     
       29. The device according to claim 21, wherein a part of a first period overlaps part of a second period, the first voltage is applied in the first period, and the second voltage is applied in the second period. 
     
     
       30. The device according to claim 21, the first memory string including:
 a first silicon material extending in a first direction crossing to a semiconductor substrate;   a first memory portion provided between the first silicon material and the first word line; and   a second memory portion provided between the first silicon material and the second word line.   
     
     
       31. The device according to claim 30, wherein the first silicon material functions as a body of the first memory cell and the second memory cell, the first memory portion is part of the first memory cell, and the second memory portion is part of the second memory cell. 
     
     
       32. The device according to claim 30, further comprising:
 a second silicon material extending in the first direction and adjacent to the first silicon material;   a first wiring connecting to one end of the first silicon material;   a second wiring connecting to one end of the second silicon material;   a sixth word line and a seventh word line arranged in the first direction, and the sixth word line being disposed in a same level as the first word line and the seventh word line being disposed in a same level as the second word line.   
     
     
       33. The device according to claim 32, further comprising:
 a connection portion connecting the second silicon material and the first silicon material; and   a second gate electrode disposed on a first insulating film;   wherein, in the erase operation, the control circuit applies a sixth voltage different from the third voltage to the second gate electrode.   
     
     
       34. The device according to claim 32, further comprising:
 a first select gate transistor having a first gate electrode, one end of the first select gate transistor connecting to the first silicon material and the other end of the first select gate transistor connecting to the first wiring;   a second select gate transistor having a third gate electrode, one end of the second select gate transistor connecting to the second silicon material and the other end of the second select gate transistor connecting to the second wiring;   wherein the control circuit applies a fourth voltage different from the third voltage to the first gate electrode in the erase operation.   
     
     
       35. The device according to claim 34, wherein, in the erase operation, the control circuit applies the third voltage to the second wiring and apply the fourth voltage to the third gate electrode. 
     
     
       36. The device according to claim 34, wherein the control circuit sets the third gate electrode and the second wiring in floating state in the erase operation. 
     
     
       37. The device according to claim 32, further comprising:
 a third silicon material extending in the first direction and adjacent to the second silicon material;   an eighth word line and a ninth word line disposed above the eighth word line, and the eighth word line disposed in a same level as the first word line and the ninth word line disposed in a same level as the second word line;   the sixth word line connecting to the eighth word line and separated from the first word line, and   the seventh word line connecting to the ninth word line and separated from the second word line.