Insulated gate turn-off device with turn-off transistor

Abstract

An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n− epi layer, a p-well, vertical insulated gate regions formed in the p-well, and n+ regions between the gate regions, so that vertical NPN and PNP transistors are formed. The device is formed of a matrix of cells. To turn the device on, a positive voltage is applied to the gate, referenced to the cathode. The cells further contain a vertical p-channel MOSFET, for shorting the base of the NPN transistor to its emitter, to turn the NPN transistor off when the p-channel MOSFET is turned on by a slight negative voltage applied to the gate. This allows the IGTO device to be more easily turned off while in a latch-up condition, when the device is acting like a thyristor.

What is claimed is: 
     
       1. An insulated gate turn-off (IGTO) device formed as a die comprising:
 a first semiconductor layer of a first conductivity type; 
 a second semiconductor layer of a second conductivity type overlying the first semiconductor layer; 
 a third semiconductor layer of the first conductivity type overlying at least a portion of the second semiconductor layer; 
 an array of cells comprising a plurality of insulated gate regions within trenches formed at least within the third semiconductor layer; 
 at least some of the cells comprising:
 a first semiconductor region of the second conductivity type overlying the third semiconductor layer and adjacent to an insulated gate region; 
 a second semiconductor region of the first conductivity type overlying the first semiconductor region and adjacent to the insulated gate region; 
 a third semiconductor region of the second conductivity type adjacent the first semiconductor region and the second semiconductor region and being more highly doped than the first semiconductor region; and 
 a first conductor shorting the second semiconductor region to the third semiconductor region, 
 wherein the first semiconductor region, the second semiconductor region, and the third semiconductor layer form a MOSFET, where a voltage applied to the insulated gate region greater than a threshold voltage of the MOSFET inverts the first semiconductor region adjacent to the insulated gate region to form a lower resistance path between the second semiconductor region and the third semiconductor layer to reduce a beta of a bipolar transistor formed by the third semiconductor region, the third semiconductor layer and the second semiconductor layer to turn off the IGTO device. 
 
 
     
     
       2. The device of  claim 1  wherein the first conductivity type is a p-type, and the second conductivity type is an n-type. 
     
     
       3. The device of  claim 1  wherein the first conductivity type is an n-type, and the second conductivity type is a p-type. 
     
     
       4. The device of  claim 1  wherein in the second semiconductor region is more highly doped than the third semiconductor layer. 
     
     
       5. The device of  claim 1  wherein the first semiconductor layer is a growth substrate. 
     
     
       6. The device of  claim 1  wherein the first semiconductor region comprises a first portion underlying a second portion, wherein the second portion is more highly doped than the first portion, wherein the second semiconductor region extends into the first portion so that the first portion is a channel region in the MOSFET. 
     
     
       7. The device of  claim 1  wherein the third semiconductor layer is formed as a well. 
     
     
       8. The device of  claim 1  wherein the first semiconductor region is formed as an epitaxial layer. 
     
     
       9. The device of  claim 1  wherein the first semiconductor region is formed as a doped region. 
     
     
       10. The device of  claim 1  wherein the third semiconductor layer has a variety of thicknesses, wherein a thickness of the third semiconductor layer below the insulated gate regions is less than a thickness of the third semiconductor layer between the insulated gate regions. 
     
     
       11. The device of  claim 1  further comprising a first electrode electrically contacting the first semiconductor layer, and a second electrode electrically contacting the second semiconductor region and the third semiconductor region, wherein the second electrode is the first conductor. 
     
     
       12. The device of  claim 11  wherein the first electrode is an anode electrode and the second electrode is a cathode electrode. 
     
     
       13. The device of  claim 1  wherein the second semiconductor region runs along a width of the insulated gate regions. 
     
     
       14. The device of  claim 1  wherein the second semiconductor region is only located near an end of the insulated gate regions. 
     
     
       15. The device of  claim 14  wherein the second semiconductor region is only located near each end of the insulated gate regions. 
     
     
       16. The device of  claim 1  wherein the second semiconductor region is only located along a middle region of the insulated gate regions. 
     
     
       17. An insulated gate device formed as a die comprising:
 a first semiconductor layer of a first conductivity type;   a second semiconductor layer of a second conductivity type overlying the first semiconductor layer;   a third semiconductor layer of the first conductivity type overlying at least a portion of the second semiconductor layer;   an array of cells comprising a plurality of insulated gate regions within trenches formed at least within the third semiconductor layer;   at least some of the cells comprising:
 a first semiconductor region of the second conductivity type overlying the third semiconductor layer; 
 a second semiconductor region of the first conductivity type overlying the first semiconductor region and adjacent to an insulated gate region; 
 a third semiconductor region of the second conductivity type adjacent the first semiconductor region and the second semiconductor region and being more highly doped than the first semiconductor region; and 
 a first conductor shorting the second semiconductor region to the third semiconductor region, 
 wherein the first semiconductor region, the second semiconductor region, and the third semiconductor layer form a MOSFET, the MOSFET having a conductivity controlled by a voltage applied to the insulated gate region, the MOSFET being configured to form a low resistance path between the second semiconductor region and the third semiconductor layer to reduce a beta of a bipolar transistor formed by the third semiconductor region, the third semiconductor layer and the second semiconductor layer to turn off the insulated gate device. 
   
     
     
       18. The device of claim 17 further comprising a first electrode electrically contacting the first semiconductor layer, and a second electrode electrically contacting the second semiconductor region and the third semiconductor region, wherein the second electrode is the first conductor. 
     
     
       19. The device of claim 17 wherein the first semiconductor region is adjacent to the insulated gate region, and the voltage applied to the insulated gate region inverts the first semiconductor region adjacent to the insulated gate region to turn off the insulated gate device.