Output driver, devices having the same, and ground termination

Abstract

An integrated circuit comprising an output driver including an output terminal, and a receiving circuit including a termination resistor connected between the output terminal and a ground. The output driver comprising a first NMOS transistor configured to pull up a voltage of the output terminal to a pull-up voltage in response to a pull-up signal, and a second NMOS transistor configured to pull down the output terminal to a ground voltage in response to a pull-down signal.

What is claimed is: 
     
       1. An integrated circuit (IC) comprising:
 an output driver including;
 an output terminal, 
 a first n-type metal-oxide semiconductor (NMOS) transistor configured to pull up a voltage of the output terminal to a pull-up voltage, in response to a pull-up signal, and 
 a second NMOS transistor configured to pull down the voltage of the output terminal to a ground voltage, in response to a pull-down signal; and 
 
 a receiving circuit including,
 a termination resistor connected between the output terminal and a ground, and 
 a sense-amplifier configured to sense and to amplify data received from the output terminal in response to a clock signal. 
 
 
     
     
       2. The IC of  claim 1 , wherein the receiving circuit includes a switch connecting the termination resistor and the ground, the switch being activated in response to a control signal. 
     
     
       3. The IC of  claim 1 , further comprising:
 a pre-driver circuit configured to, in response to an enable signal, generate the pull-up signal and the pull-down signal in response to an enable signal and in response to output such that the pull-up signal and the pull-down signal are based on data, the pull-up signal and the pull-down signal being complementary to each other; and 
 a control circuit configured to decode a command and to control activation of one of the enable signal and transmission of the clock signal based on a decoding result. 
 
     
     
       4. A system comprising:
 a first data processing circuit including,
 a first output driver having a first output terminal connected to a channel, and 
 a first receiving circuit, the first receiving circuit including a first sense amplifier configured to sense and to amplify first input data input through the first output terminal in response to a first clock signal; and 
 
 a second data processing circuit configured to communicate with the first data processing circuit via the channel, wherein 
 the first output driver including includes,
 a first n-type metal-oxide semiconductor (NMOS) transistor configured to pull up a voltage of the first output terminal to a pull-up voltage of the first data processing circuit in response to a first pull-up signal, and 
 a second NMOS transistor configured to pull down a voltage of the first output terminal to a ground voltage of the first data processing circuit in response to a first pull-down signal, 
 the second data processing circuit including includes a second receiving circuit, the second receiving circuit including a first termination resistor connected between the channel and a ground of the second data processing circuit. 
 
 
 
     
     
       5. The system of  claim 4 , wherein
 the first receiving circuit associated with the first data processing circuit includes a second termination resistor connected between the channel and a ground of the first data processing circuit, 
 the second data processing circuit further includes a second output driver having a second output terminal connected to the channel, the second output driver includes including,
 a third NMOS transistor configured to pull up a voltage of the second output terminal to a pull-up voltage of the second data processing circuit in response to a second pull-up signal; and 
 a fourth NMOS transistor configured to pull down the voltage of the second output terminal to a ground voltage of the second data processing circuit in response to a second pull-down signal. 
 
 
     
     
       6. The system of  claim 4 , wherein
 the first data processing circuit includes,
 a first pre-driver circuit configured to generate the first pull-up signal and the first pull-down signal in response to such that the first pull-up signal and the first pull-down signal are based on first output data, and the first pull-up signal and the first pull-down signal being are complementary to each other, and 
 
 the second data processing circuit includes,
 a second pre-driver circuit configured to generate the second pull-up signal and the second pull-down signal, in response to such that the second pull-up signal and the second pull down signal are based on second output data, and the second pull-up signal and the second pull-down signal being are complementary to each other; and 
 the second receiving circuit including a second sense amplifier configured to sense and to amplify second input data input through the second output terminal in response to a second clock signal. 
 
 
     
     
       7. The system of  claim 6 , wherein the channel is a bidirectional data bus. 
     
     
       8. The system of  claim 4 , wherein the channel is configured to transmit optical signals. 
     
     
       9. The system of  claim 4 , wherein the first data processing circuit further comprises:
 a first pre-driver circuit configured to generate, in response to a first enable signal, the first pull-up signal and the first pull-down signal, in response to a first enable signal and  such that the first pull-up signal and the first pull-down signal are based on first output data, and the first pull-up signal and the first pull-down signal being are complementary to each other; and 
 a first control circuit configured to decode a first command and to control activation of the first enable signal or transmission of the first clock signal according to a decoding result. 
 
     
     
       10. The system of  claim 9 , wherein the second data processing circuit further comprises:
 a second pre-driver circuit configured to generate, in response to a second enable signal, the second pull-up signal and the second pull-down signal, in response to a second enable signal and such that the second pull-up signal and the second pull-down signal are based on second output data, and the second pull-up signal and the second pull-down signal being are complementary to each other; 
 a second sense-amplifier configured to sense and to amplify second input data input through the second output terminal, in response to a second clock signal; and 
 a second control circuit configured to decode a second command and to control activation of the second enable signal or transmission of the a second clock signal according to a decoding result, wherein
 the second receiving circuit includes a second sense-amplifier configured to sense and to amplify second input data that is input through the second output terminal, in response to the second clock signal. 
 
 
     
     
       11. The system of  claim 4 , wherein the system is a system-on chip. 
     
     
       12. The system of  claim 4 , wherein the first data processing circuit is a master configured to use a serial communication protocol and the second data processing circuit is a slave configured to use the serial communication protocol. 
     
     
       13. The system of  claim 4 , wherein the system is a multi-chip package. 
     
     
       14. The system of  claim 4 , wherein
 the first data processing circuit and the second data processing circuit are mounted on a board, and 
 the system is a memory module. 
 
     
     
       15. The system of  claim 4 , further comprising:
 a central processing unit (CPU) configured to communicate with the first data processing circuit and the second data processing circuit through a data bus, wherein the system is any one of a personal computer (PC), a laptop computer and a handheld device. 
 
     
     
       16. An integrated circuit (IC) comprising:
 a first n-type metal-oxide semiconductor (NMOS) transistor configured to pull up a voltage of an output terminal to a pull-up voltage in response to a pull-up signal;   a second NMOS transistor configured to pull down the voltage of the output terminal to a ground voltage in response to a pull-down signal;   a selection circuit configured to selectively output one of first data and second data in response to a clock signal;   a first pre-driver circuit configured to output the pull-up signal in response to output data of the selection circuit; and   a second-pre-driver circuit configured to output the pull-down signal in response to the output data of the selection circuit,   wherein the pull-up signal and the pull-down signal are complementary to each other.   
     
     
       17. The IC of  claim 16 , further comprising:
 a resistance circuit connected between the output terminal and a data pad.   
     
     
       18. The IC of  claim 16 , wherein a difference between a threshold voltage of the first NMOS transistor and a threshold voltage of the second NMOS transistor is 50 mV to 100 mV. 
     
     
       19. The IC of  claim 16 , further comprising:
 a control signal generation circuit configured to generate a control signal in response to the clock signal and the pull-down signal; and   a third NMOS transistor configured to pull down the voltage of the output terminal to the ground voltage in response to the control signal.   
     
     
       20. The IC of  claim 16 , further comprising:
 a control signal generation circuit configured to determine dependency of the pull-down signal input at each time point in response to the clock signal and to generate a control signal according to a determination result; and   a third NMOS transistor configured to pull down the voltage of the output terminal to the ground voltage in response to the control signal.   
     
     
       21. An integrated circuit (IC) comprising:
 an output driver including,
 an output terminal, 
 a first n-type metal-oxide semiconductor (NMOS) transistor configured to pull up a voltage of the output terminal to a pull-up voltage, in response to a pull-up signal, and 
 a second NMOS transistor configured to pull down the voltage of the output terminal to a ground voltage, in response to a pull-down signal; and 
   a receiving circuit including,
 a termination resistor connected between the output terminal and a ground, and 
 a sense-amplifier configured to sense and to amplify data received from the output terminal in response to a clock signal, the sense-amplifier including a first p-type metal-oxide semiconductor (PMOS) transistor and a second PMOS transistor, the gate node of the first PMOS transistor being connected to the output terminal and the gate node of the second PMOS transistor being connected to a reference voltage, and a cross coupled latch connected to drain node of the first PMOS transistor and drain node of the second PMOS transistor respectively. 
   
     
     
       22. The IC of claim 21, wherein the cross coupled latch is configured to store data received from the output terminal during a first phase of the clock signal. 
     
     
       23. The IC of claim 22, wherein the cross coupled latch is configured to be reset during a second phase of the clock signal. 
     
     
       24. The IC of claim 21, wherein the cross coupled latch comprises:
 a third PMOS transistor, the source node of the third PMOS transistor being connected to the drain node of the second PMOS transistor and the gate node and the drain node of the third PMOS transistor being connected a second data out node and a first data out node respectively;   a fourth PMOS transistor, the source node of the fourth PMOS transistor being connected to the drain node of the first PMOS transistor and the gate node and the drain node of the fourth PMOS transistor being connected the first data out node and the second data out node respectively;   a third NMOS transistor, the source node of the third NMOS transistor being connected to a ground voltage VSSQ and the gate node and the drain node of the third NMOS transistor being connected to the second data out node and the first data out node respectively; and   a fourth NMOS transistor, the source node of the fourth NMOS transistor being connected to the ground voltage VSSQ and the gate node and the drain node of the fourth NMOS transistor being connected to the first data out node and the second data out node respectively.   
     
     
       25. The IC of claim 24, wherein the sense amplifier further comprises:
 a fifth NMOS transistor, the source node of the fifth NMOS transistor being connected to the ground voltage VSSQ and the gate node and the drain node of the fifth NMOS transistor being connected to the clock signal and the first data out node respectively; and   a sixth NMOS transistor, the source node of the sixth NMOS transistor being connected to the ground voltage VSSQ and the gate node and the drain node of the sixth NMOS transistor being connected to the clock signal and the second data out node respectively.   
     
     
       26. An integrated circuit (IC) comprising:
 an output driver including an output terminal, a first n-type metal-oxide semiconductor (NMOS) transistor configured to pull up a voltage of the output terminal to a pull-up voltage, in response to a pull-up signal, and a second NMOS transistor configured to pull down the voltage of the output terminal to a ground voltage, in response to a pull-down signal; and   a receiving circuit including,
 a termination resistor connected between the output terminal and a ground, and 
   a sense-amplifier configured to sense and to amplify data received from the output terminal in response to a clock signal, the sense-amplifier including,
 a first PMOS transistor, the gate node of the first PMOS transistor being connected to the clock signal, and the source node of the first PMOS transistor being connected to a power supply voltage VDDQ; 
 a second PMOS transistor, the gate node of the second PMOS transistor being connected to the output terminal, and the source node of the second PMOS transistor being connected to the drain node of the first PMOS transistor; 
 a third PMOS transistor, the gate node of the third PMOS transistor being connected to a reference voltage, and the source node of the third PMOS transistor being connected to the drain node of the first PMOS transistor; 
 a fourth PMOS transistor, the source node of the fourth PMOS transistor being connected to the drain node of the second PMOS transistor, and the gate node and the drain node of the fourth PMOS transistor being connected a first data out node and a second data out node, respectively; 
 a fifth PMOS transistor, the source node of the fifth PMOS transistor being connected to the drain node of the third PMOS transistor, and the gate node and the drain node of the fifth PMOS transistor being connected the second data out node and the first data out node, respectively; 
 a third NMOS transistor, the source node of the third NMOS transistor being connected to a ground voltage VSSQ, and the gate node and the drain node of the third NMOS transistor being connected to the second data out node and the first data out node, respectively; and 
 a fourth NMOS transistor, the source node of the fourth NMOS transistor being connected to the ground voltage VSSQ, and the gate node and the drain node of the fourth NMOS transistor being connected to the first data out node and the second data out node, respectively. 
   
     
     
       27. The IC of claim 26, wherein the sense amplifier further comprises:
 a fifth NMOS transistor, the source node of the fifth NMOS transistor being connected to the ground voltage VSSQ, and the gate node and the drain node of the fifth NMOS transistor being connected to the clock signal and the first data out node, respectively; and   a sixth NMOS transistor, the source node of the sixth NMOS transistor being connected to the ground voltage VSSQ, and the gate node and the drain node of the sixth NMOS transistor being connected to the clock signal and the second data out node, respectively.