Performance and power optimization via block oriented performance measurement and control

Abstract

An integrated circuit includes a plurality of functional blocks. Utilization information for the various functional blocks is generated. Based on that information, the power consumption and thus the performance levels of the functional blocks can be tuned. Thus, when a functional block is heavily loaded by an application, the performance level and thus power consumption of that particular functional block is increased. At the same time, other functional blocks that are not being heavily utilized and thus have lower performance requirements can be kept at a relatively low power consumption level. Thus, power consumption can be reduced overall without unduly impacting performance.

What is claimed is: 
     
       1. A method of controlling power consumption in an integrated circuit that includes a plurality of functional blocks, comprising:
 generating respective block utilization information for the functional blocks included in the integrated circuit; and   independently managing power of the respective functional blocks to match respective block utilization levels according to the respective block utilization information.   
     
     
       2. The method as recited in  claim 1  wherein the operation of managing power includes independently adjusting frequency of clocks being respectively supplied to the functional blocks according to the block utilization information. 
     
     
       3. The method as recited in  claim 1  wherein the operation of managing power includes adjusting a voltage being supplied to one of the functional blocks independently of voltages being supplied to other functional blocks according to the utilization information of the one functional block. 
     
     
       4. The method as recited in  claim 1  A method of controlling power consumption in an integrated circuit that includes a plurality of functional blocks, comprising:
 generating respective block utilization information for the functional blocks included in the integrated circuit; and 
 independently managing power of the respective functional blocks to match respective block utilization levels according to the respective block utilization information, wherein the operation of managing power includes adjusting decreasing a dispatch rate of operations to at least a section of one of the functional blocks according to the block utilization information a decrease in the block utilization level associated with the one functional block. 
 
     
     
       5. The method as recited in  claim 1  wherein the block utilization information from one of the functional blocks provides an indication of what percentage of time the one functional block is being used. 
     
     
       6. The method as recited in  claim 1  wherein the block utilization information from one of the functional blocks provides dispatch information relating to how many operations have been dispatched to or within the functional block. 
     
     
       7. The method as recited in  claim 1  wherein the functional blocks include at least one of a fixed point unit, an arithmetic logic unit, a floating point unit, a barrel shifter, a load/store unit, a memory controller, an input/output interface unit and a cache. 
     
     
       8. The method as recited in  claim 1  wherein the utilization information indicates how much time the functional block spends idling. 
     
     
       9. The method as recited in  claim 1  further comprising monitoring block utilization on a task basis. 
     
     
       10. The method as recited in  claim 9  further comprising adjusting power consumption of at least one of the functional blocks when a task switch occurs from a first task to a second task according to the block utilization information for the one functional block corresponding to the second task. 
     
     
       11. The method as recited in  claim 1  further comprising:
 reading utilization information from a utilization register associated with one of the functional blocks; and 
 adjusting power usage of the one functional block according to the utilization information read. 
 
     
     
       12. The method as recited in  claim 1  further comprising comparing utilization information related to one of the blocks to at least one threshold value to determine whether to adjust power usage. 
     
     
       13. The method as recited in  claim 1  further comprising:
 adjusting the frequency of a first clock being supplied to one of the functional blocks upward, when first utilization information for the one block is above a first threshold; and 
 adjusting the frequency of the first clock downward when the first utilization information for the one block is below a second threshold. 
 
     
     
       14. The method as recited in  claim 1  further periodically checking utilization information for a plurality of the functional blocks. 
     
     
       15. The method as recited in  claim 1  further comprising checking utilization information on a periodic basis for at least one of the functional blocks to determine whether to adjust power consumption of the one functional block to reflect current utilization information. 
     
     
       16. An integrated circuit comprising:
 a plurality of functional blocks;   utilization circuits respectively associated with the functional blocks coupled to provide block utilization information of the functional blocks; and wherein   the integrated circuit is responsive to the block utilization information to independently adjust power consumption levels of the functional blocks to match respective block utilization levels.   
     
     
       17. The integrated circuit as recited in  claim 16  wherein at the power consumption levels of the functional blocks are determined at least in part by independently adjustable clock frequencies of respective clocks being supplied to the functional blocks. 
     
     
       18. The integrated circuit as recited in  claim 17  wherein the power consumption levels of the functional blocks are determined at least in part according to independently controllable voltages being supplied to respective ones of the functional blocks. 
     
     
       19. The integrated circuit as recited in  claim 16  further comprising:
 a clock control circuit coupled to independently adjust the frequency of respective clocks being supplied to the functional blocks. 
 
     
     
       20. The integrated circuit as recited in  claim 16  further comprising registers associated with respective utilization circuits of the functional blocks containing block utilization information. 
     
     
       21. The integrated circuit as recited in  claim 16  wherein the utilization circuits are software accessible. 
     
     
       22. The integrated circuit as recited in  claim 16  further including software operable on the integrated circuit to read utilization information of a selected functional block and to control at least one power performance parameter of the selected functional block in response thereto. 
     
     
       23. A computer system comprising:
 an integrated circuit that includes a plurality of functional blocks;   utilization circuits respectively associated with the functional blocks and coupled to provide block utilization information of the functional blocks; and   a computer program including an instruction sequence executable by the integrated circuit to adjust power consumption levels of the functional blocks to match respective block utilization levels according to the block utilization information.   
     
     
       24. The computer system as recited in  claim 23  wherein the computer program tracks utilization information for each of the functional blocks on a task basis. 
     
     
       25. The computer system as recited in  claim 24  wherein the computer program is responsive to a task switch from a first task to a second task to adjust power management parameters for one or more of the functional blocks according to utilization information corresponding to the second task. 
     
     
       26. An electronic system comprising:
 an integrated circuit including a plurality of functional blocks;   means for determining respective block utilization information of the functional blocks; and   means for adjusting power consumption of the respective functional blocks to match respective block utilization levels according to the respective block utilization information.   
     
     
       27. The method of  claim 1 , wherein the independently managing power of the respective block functional blocks to match respective block utilization levels comprises:
 increasing power consumption levels for those functional blocks with utilization information that indicates increased utilization; and   decreasing power consumption levels for those functional blocks with utilization information that indicates decreased utilization.   
     
     
       28. The method of claim 4, wherein the operation of managing power further includes increasing the dispatch rate of operations to the section of the one functional block according to an increase in the utilization level associated with the one functional block. 
     
     
       29. The method of claim 4, wherein the dispatch rate of operations relates to how many operations have been dispatched to or within the one functional block over a period of time. 
     
     
       30. A computer system comprising:
 an integrated circuit that includes a plurality of functional blocks;   utilization circuits respectively coupled to the functional blocks to provide block utilization information of the functional blocks; and   a computer program including an instruction sequence executable by the integrated circuit to adjust power consumption levels of the functional blocks to match respective block utilization levels according to the block utilization information,   wherein, in response to the block utilization level of a respective functional block being greater than a first threshold, the computer program causes a power supply voltage received by the respective functional block to increase and a clock frequency of a clock received by the respective functional block to increase,   wherein, in response to the block utilization level of the respective functional block being less than a second threshold, the computer program causes the clock frequency of the clock received by the respective functional block to decrease and the power supply voltage received by the respective functional block to decrease,   and wherein the second threshold is less than the first threshold.   
     
     
       31. The computer system of claim 30, wherein:
 in response to the block utilization level of the respective functional block being greater than the first threshold, the computer program causes an increase in a dispatch rate of instructions issued to the respective functional block, and   in response to the block utilization level of the respective functional block being less than the second threshold, the computer program causes a decrease in the dispatch rate of instructions issued to the respective functional block.   
     
     
       32. The computer system of claim 30, wherein the computer program causes the clock frequency of the clock received by the respective functional block to be adjusted without changing a clock frequency of a clock received by another functional block. 
     
     
       33. The computer system of claim 30, wherein:
 a first block utilization level is associated with the block utilization level of the respective functional block being above the first threshold, a second block utilization level is associated with the block utilization level of the respective functional block being between the first and second thresholds, and a third block utilization level is associated with the block utilization level of the respective functional block being below the second threshold, and   the respective functional block operating at the third block utilization level has a clock frequency greater than zero hertz.   
     
     
       34. The computer system of claim 30, wherein:
 in response to the block utilization level of the respective functional block being greater than the first threshold, the power supply voltage is increased prior to the clock frequency being increased, and   in response to the block utilization level of the respective functional block being less than the second threshold, the clock frequency is decreased prior to the power supply voltage being decreased.   
     
     
       35. A computer system comprising:
 a memory;   an integrated circuit that includes a plurality of functional blocks;   utilization circuits respectively coupled to the functional blocks to provide block utilization information of the functional blocks, wherein the block utilization information represents activity in each of the functional blocks as measured over a period of time, and wherein each of the utilization circuits comprises:
 a utilization detection circuit to detect a utilization event; 
 a utilization counter to count a number of utilization events; and 
 a cycle counter to count to a value equal to the period of time; and 
   a computer program including an instruction sequence executable by the integrated circuit to adjust power consumption levels of the functional blocks to match respective block utilization levels according to the block utilization information,   wherein one or more of the block utilization levels are based at least in part on the number of utilization events counted by the utilization counter over the period of time,   wherein, in response to an increase in a block utilization level for a respective functional block, a clock frequency of the respective functional block is increased to a first frequency value, and   wherein, in response to a decrease in the block utilization level for the respective functional block, the clock frequency of the respective functional block is decreased to a second frequency value, the first and second frequency values being different from one another and each greater than zero hertz.   
     
     
       36. The computer system of claim 35, wherein the clock frequency increases or decreases in step adjustments. 
     
     
       37. The computer system of claim 35, wherein the memory comprises a system memory. 
     
     
       38. The computer system of claim 35, wherein the clock frequency of the respective functional block is increased to the first frequency value or decreased to the second frequency value without changing a clock frequency of at least one other functional block. 
     
     
       39. The computer system of claim 35, wherein:
 the first frequency value matches a first block utilization level associated with a first load of the respective functional block; and   the second frequency matches a second block utilization level associated with a second load of the respective functional block, wherein the first load is greater than the second load.   
     
     
       40. The computer system of claim 35, wherein:
 in response to the increase in the block utilization level for the respective functional block, a power supply voltage of the respective functional block is increased to a first voltage value, and   in response to the decrease in the block utilization level for the respective functional block, the power supply voltage of the respective functional block is decreased to a second voltage value, the first and second voltage values being different from one another and each greater than zero volts.   
     
     
       41. The computer system of claim 35, wherein:
 in response to the increase in the block utilization level for the respective functional block, a dispatch rate of instructions issued to the respective functional block is increased to a first dispatch rate value, and   in response to the decrease in the block utilization level for the respective functional block, the dispatch rate of instructions issued to the respective functional block is decreased to a second dispatch rate value, the first and second dispatch values being different from one another and each greater than zero.   
     
     
       42. An integrated circuit comprising:
 a plurality of functional blocks;   utilization circuits respectively coupled to the functional blocks to provide block utilization information of the functional blocks, wherein the block utilization information represents activity in each of the functional blocks as measured over a period of time, and   wherein each of the utilization circuits comprises:
 a utilization detection circuit to detect a utilization event; 
 a utilization counter to count a number of utilization events; and 
 a cycle counter to count to a value equal to the period of time; 
   wherein the integrated circuit, responsive to the block utilization information, independently adjusts power consumption levels of the of the functional blocks to match respective block utilization levels according to the block utilization information,   wherein one or more of the block utilization levels are based at least in part on the number of utilization events counted by the utilization counter over the period of time,   wherein, in response to an increase in a block utilization level for a respective functional block, a clock frequency of the respective functional block is increased to a first frequency value, and   wherein, in response to a decrease in the block utilization level for the respective functional block, the clock frequency of the respective functional block is decreased to a second frequency value, the first and second frequency values being different from one another and each greater than zero hertz.   
     
     
       43. The integrated circuit of claim 42, wherein the clock frequency increases or decreases in step adjustments. 
     
     
       44. The integrated circuit of claim 42, wherein the clock frequency of the respective functional block is increased to the first frequency value or decreased to the second frequency value without changing a clock frequency of at least one other functional block. 
     
     
       45. The integrated circuit of claim 42, wherein:
 the first frequency value matches a first block utilization level associated with a first load of the respective functional block; and   the second frequency matches a second block utilization level associated with a second load of the respective functional block, wherein the first load is greater than the second load.   
     
     
       46. The integrated circuit of claim 42, wherein:
 in response to the increase in the block utilization level for the respective functional block, a power supply voltage of the respective functional block is increased to a first voltage value, and   in response to the decrease in the block utilization level for the respective functional block, the power supply voltage of the respective functional block is decreased to a second voltage value, the first and second voltage values being different from one another and each greater than zero volts.   
     
     
       47. The integrated circuit of claim 42, wherein:
 in response to the increase in the block utilization level for the respective functional block, a dispatch rate of instructions issued to the respective functional block is increased to a first dispatch rate value, and   in response to the decrease in the block utilization level for the respective functional block, the dispatch rate of instructions issued to the respective functional block is decreased to a second dispatch rate value, the first and second dispatch values being different from one another and each greater than zero.