Variable resistance memory device

Abstract

A variable resistance memory device includes a plurality of column selection switches, a plurality of variable resistance memory cells configured to be stacked and selected by the plurality of column selection switches, and a bit line connected to the plurality of variable resistance memory cells. Each of the plurality of variable resistance memory cells includes an ovonic threshold switch (OTS) element selectively driven by a plurality of word lines arranged to be stacked and a variable resistor connected in parallel to the OTS element.

What is claimed is: 
     
       1. A variable resistance memory device, comprising:
 a semiconductor substrate; 
 a common source line formed on the semiconductor substrate; 
 a column selection switch formed on the semiconductor substrate; 
 an ohmic layer formed on the column selection switch; 
 stacked gates formed on the column selection switch, wherein the stacked gates include a plurality of conductive layers that are stacked to be insulated from one another; 
 an ovonic threshold switch (OTS) material layer formed on a sidewall of a hole penetrating through the stacked gates and connected to the column selection switch via the ohmic layer; and 
 a variable resistance material layer formed on a surface of the OTS material layer; 
 a buried insulating layer filling a remaining central portion of the hole; 
 a gate insulating layer formed between the OTS material layer and the sidewall of the stacked gates, and 
 a bit line formed on top of the stack gates to be in contact with top respective surfaces of the OTS material layer, the variable resistance material layer and the buried insulating layer, 
 wherein the OTS material layer overlaps with selected stacked gates and has superior conductivity and current mobility to the variable resistance material layer, and 
 wherein a current from the bit line to the common source line flows along a portion of the OTS material layer corresponding to selected gates and a portion of the variable resistance layer corresponding to an unselected gate. 
 
     
     
       2. The variable resistance memory device of  claim 1 , wherein the column selection switch includes a vertical channel transistor,
 wherein the vertical channel transistor includes: 
 a common source region formed on the semiconductor substrate; 
 a channel pillar formed on the common source region; 
 a drain formed in an upper region of the channel pillar; 
 a gate surrounding an outer circumference of the channel pillar; and 
 a first gate insulating layer interposed between the channel pillar and the gate. 
 
     
     
       3. The variable resistance memory device of  claim 2 , wherein the stacked gates are formed to be disposed at either side of the drain. 
     
     
       4. The variable resistance memory device of  claim 2 , wherein the OTS material layer is formed on the drain of the vertical channel transistor. 
     
     
       5. The variable resistance memory device of  claim 4 , wherein the OTS material layer includes at least one selected from the group of tellurium (Te), selenium (Se), germanium (Ge), silicon (Si), arsenic (As), titanium (Ti), sulfur (S), and antimony (Sb), and wherein the OTS material layer has a negative differential resistance (NDR) characteristic. 
     
     
       6. The variable resistance memory device of  claim 1 , wherein the variable resistance material layer includes a PCMO (Pr 0.7 Ca 0.3 MnO 3 ) layer that is a material for a ReRAM, a chalcogenide layer that is a material for a PCRAM, a magnetic layer that is a material for a MRAM, a magnetization reversal device layer that is a material for a spin-transfer torque magnetoresistive RAM (STTMRAM), or a polymer layer that is a material for a PoRAM. 
     
     
       7. A variable resistance memory device, comprising:
 a semiconductor substrate; and 
 a plurality of memory cells stacked on the semiconductor substrate and connected to one another in series between a bit line and a common source line, wherein each of the plurality of memory cells includes an ovonic threshold switch (OTS) and a variable resistance layer, 
 wherein the OTS includes OTSs include a plurality of gates stacked to be insulated from each other and an OTS material layer formed to overlap the plurality of gates, and the OTS is configured to be turned on based on selection of the plurality of gates, 
 wherein a current from the bit line to the common source line flows along a portion of the OTS material layer corresponding to selected gates and a portion of the variable resistance layer corresponding to an unselected gate, and 
 wherein the OTS material layer overlaps with the selected gates and has superior conductivity and current mobility to the variable resistance layer. 
 
     
     
       8. The variable resistance memory device of  claim 7 , wherein the OTS and the variable resistance layer are connected in parallel to each other. 
     
     
       9. A variable resistance memory device, comprising:
 a plurality of column selection switches connected to a common source line;   a plurality of variable resistance memory cells configured to be stacked, and to be selected by the plurality of column selection switches; and   a bit line connected to the plurality of variable resistance memory cells,   wherein each of the plurality of variable resistance memory cells includes an ovonic threshold switch (OTS) element selectively driven by a plurality of word lines that is stacked and a variable resistor connected in parallel to the OTS element.   
     
     
       10. A variable resistance memory device, comprising:
 a plurality of gate structures stacked over insulating layers in an alternate manner;   a gate insulating layer formed on sidewalls of the plurality of gate structures;   an ovonic threshold switch (OTS) material layer formed on a surface of the gate insulating layer; and   a resistance layer formed on a surface of an OTS material layer,   wherein the OTS material layer overlaps with selected gate structures and has superior conductivity and current mobility to the resistance layer, and   wherein a current from the bit line to the common source line flows along a portion of the OTS material layer corresponding to selected gate structures and a portion of the variable resistance layer corresponding to an unselected gate structure.   
     
     
       11. The variable resistance memory device of claim 10,
 wherein the OTS material layer includes at least one selected from the group of tellurium (Te), selenium (Se), germanium (Ge), silicon (Si), arsenic (As), titanium (Ti), sulfur (S), and antimony (Sb), and   wherein the OTS material layer has a negative differential resistance (NDR) characteristic.   
     
     
       12. The variable resistance memory device of claim 10,
 wherein the resistance layer includes a PCMO (Pr 0.7 Ca 0.3 MnO 3 ) layer that is a material for a ReRAM, a chalcogenide layer that is a material for a PCRAM, a magnetic layer that is a material for a MRAM, a magnetization reversal device layer that is a material for a spin-transfer torque magnetoresistive RAM (STTMRAM), or a polymer layer that is a material for a PoRAM.   
     
     
       13. A variable resistance memory device, comprising:
 a plurality of gate structures stacked over insulating layers in an alternate manner;   a gate insulating layer formed on sidewalls of the plurality of gate structures;   a first chalcogenide layer formed on a surface of the gate insulating layer; and   a second chalcogenide layer formed on a surface of the first chalcogenide layer,   wherein the first chalcogenide layer overlaps with selected gate structures and has superior conductivity and current mobility to the second chalcogenide layer, and   wherein a current from the bit line to the common source line flows along a portion of the first chalcogenide layer corresponding to selected gate structures and a portion of the second chalcogenide layer corresponding to an unselected gate structure.   
     
     
       14. The variable resistance memory device of claim 13, wherein a resistance of the first chalcogenide layer corresponding to a selected gate structure is changed by a voltage of the selected gate structure. 
     
     
       15. The variable resistance memory device of claim 14, wherein the first chalcogenide layer is an ovonic threshold switch (OTS) material layer. 
     
     
       16. The variable resistance memory device of claim 14,
 wherein the first chalcogenide layer contains at least one selected from the group consisting of tellurium (Te), selenium (Se), germanium (Ge), silicon (Si), arsenic (As), titanium (Ti), sulfur (S), and antimony (Sb).   
     
     
       17. A method of fabricating a variable resistance memory device, the method comprising:
 alternately forming a plurality of insulating layers and a plurality of gate layers alternately one by one on a semiconductor substrate having a conductive region, to form a stack structure comprising a plurality of gate structures connected in series;   etching the plurality of insulating layers and the plurality of gate layers to expose the conductive region thereby forming a hole in the stack structure;   forming a gate insulating layer on a sidewall of the hole;   forming an ovonic threshold switch (OTS) material layer on a surface of the gate insulating layer;   forming a resistance layer on a surface of the OTS material layer,   and filling a buried insulating layer in the hole in which the resistance layer is formed,   wherein the OTS material layer overlaps with selected gate layers and has superior conductivity and current mobility to the resistance layer.   
     
     
       18. The method of claim 17, further comprising,
 forming a common source line on a substrate;   forming a column selection transistor in contact with the common source line and in contact with the OTS material layer and the resistance layer;   planarizing the buried insulating layer, the resistance layer and the OTS material layer to expose an uppermost insulating layer;   forming a bit line on the resulting structure in contact with the OTS material layer and the resistance layer,   wherein in operation a current flows from the bit line to the common source line along a portion of the OTS material layer corresponding to selected gate structures and a portion of the resistance layer corresponding to an unselected gate structure.