Clock generation circuit with fast-startup standby mode

Abstract

A clock generation circuit operates in a STANDBY mode as well as conventional OFF and ON modes. In STANDBY mode, a small pre-bias current is applied to amplifiers in the clock generation circuit, which bias voltages on internal nodes to very near their operating voltage values. This reduces transient perturbations on signals as the clock generation circuit is returned to ON mode. The smaller transients settle faster, and allow the clock generation circuit to achieve very fast startup times from STANDBY to ON. The very fast startup times allow the clock generation circuit to be placed in STANDBY mode more often, such as when a system must monitor and rapidly respond to activity on an external bus or interface (such as an RF modem).

What is claimed is: 
     
       1. A method of operating a clock generation circuit on an integrated circuit, the clock generation circuit including an oscillator circuit, comprising:
 monitoring clock request indicators from one or more circuits; 
 if at least one circuit requests a an associated clock signal, operating the clock generation circuit in a first, full power mode in which the clock generation circuit outputs at least one clock signal; 
 if no circuit requests a an associated clock signal, determining whether a second, sleep mode is allowed, in which the oscillator circuit is disabled and the clock generation circuit outputs no clock signal;
 if the second, sleep mode is allowed, operating the clock generation circuit in the second, sleep mode; 
 if the second, sleep mode is not allowed, operating the clock generation circuit in a third, standby mode in which one or more circuit nodes in the clock generation circuit are biased near their operating voltages but the oscillator circuit does not oscillate and the clock generation circuit outputs no clock signal. 
 
 
     
     
       2. The method of  claim 1  further comprising, when the clock generation circuit is in the third, standby mode:
 detecting at least one clock request indication; 
 in response to detecting at least one clock request indication, transitioning the clock generation circuit from the third, standby mode to the first, full power mode; 
 wherein a start-up time from detecting at least one clock request indication to outputting a stable clock signal is less than 10 usec. 
 
     
     
       3. The method of  claim 2  wherein the start-up time is less than 2 usec. 
     
     
       4. The method of  claim 1  wherein power consumption of the clock generation circuit in the third, standby mode is at least 50% less than in the first, full power mode. 
     
     
       5. The method of  claim 4  wherein power consumption of the clock generation circuit in the third, standby mode is at least 90% less than in the first, full power mode. 
     
     
       6. The method of  claim 1  wherein the clock generation circuit has separate first and second enable inputs, and wherein
 operating the clock generation circuit in the first, full power mode comprises asserting both first and second enable signals applied to the first and second enable inputs, respectively; 
 operating the clock generation circuit in the second, sleep mode comprises deasserting both of the first and second enable signals; and 
 operating the clock generation circuit in the third, standby mode comprises asserting the first enable signal and deasserting the second enable signal. 
 
     
     
       7. The method of  claim 1  wherein
 operating the clock generation circuit in the first, full power mode comprises providing a first bias current to the clock generation circuit; 
 operating the clock generation circuit in the second, sleep mode comprises providing no bias current to the clock generation circuit; and 
 operating the clock generation circuit in the third, standby mode comprises providing a second bias current, less than the first bias current, to the clock generation circuit. 
 
     
     
       8. The method of  claim 7  wherein the second bias current is about 10% of the first bias current or less. 
     
     
       9. The method of  claim 1  wherein the oscillator circuit is an RC oscillator. 
     
     
       10. The method of  claim 1  wherein the oscillator circuit is a relaxation oscillator. 
     
     
       11. A clock generation circuit, comprising:
 an oscillator circuit operative to selectively generate a periodic signal; 
 an output circuit receiving a the periodic signal from the oscillator circuit and operative to selectively output at least one clock signal; 
 a bias circuit operative to control the clock generation circuit to operate in one of three modes, selected from the group consisting of
 a first, full power mode in which the output circuit outputs the at least one clock signal; 
 a second, sleep mode in which the oscillator circuit is disabled and the output circuit outputs no clock signal; and 
 a third, standby mode in which nodes within the oscillator circuit and output circuit are biased near their operating voltages but the oscillator circuit does not oscillate and the output circuit outputs no clock signal. 
 
 
     
     
       12. The clock generation circuit of  claim 11  further comprising at least one control input, and wherein, in response to one or more signals received at the at least one control input, the clock generation circuit is operative to transition from the third, standby mode to the first, full power mode, and wherein a start-up time from the one or more control signals to outputting a stable clock signal is less than 10 usec. 
     
     
       13. The clock generation circuit of  claim 12  wherein the start-up time is less than 2 usec. 
     
     
       14. The clock generation circuit of  claim 11  wherein power consumption of the clock generation circuit in the third, standby mode is at least 50% less than in the first, full power mode. 
     
     
       15. The clock generation circuit of  claim 14  wherein power consumption of the clock generation circuit in the third, standby mode is at least 90% less than in the first, full power mode. 
     
     
       16. The clock generation circuit of  claim 12  wherein the at least one control input comprises separate first and second enable inputs, and wherein the bias circuit is operative to
 operate the clock generation circuit in the first, full power mode in response to both first and second enable signals received at the first and second enable inputs, respectively, being asserted; 
 operate the clock generation circuit in the second, sleep mode in response to both first and second enable signals being deasserted; and 
 operating the clock generation circuit in the third, standby mode in response to the first enable signal being asserted and the second enable signal being deasserted. 
 
     
     
       17. The clock generation circuit of  claim 11  wherein the bias circuit is operative to
 operate the clock generation circuit in the first, full power mode by providing a first bias current to the clock generation circuit; 
 operate the clock generation circuit in the second, sleep mode by providing no bias current to the clock generator circuit; and 
 operate the clock generation circuit in the third, standby mode by providing a second bias current, less than the first bias current, to the clock generation circuit. 
 
     
     
       18. The clock generation circuit of  claim 17  wherein the second bias current is about 10% of the first bias current or less. 
     
     
       19. The clock generation circuit of  claim 11  wherein the oscillator circuit is an RC oscillator. 
     
     
       20. The clock generation circuit of  claim 11  wherein the oscillator circuit is a relaxation oscillator. 
     
     
       21. A clock generation circuit comprising:
 an oscillator circuit including an amplifier and operative to selectively generate a periodic signal;   a bias circuit connected to the amplifier; and   an output circuit receiving the periodic signal from the oscillator circuit and operative to output a clock signal;   wherein the clock generation circuit is adapted to operate in one of a first full power mode, a second sleep mode or a third standby mode, dependent on an indication provided for the clock generation circuit; wherein
 in the first full power mode, the oscillator circuit provides the periodic signal to the output circuit and the output circuit generates the clock signal; 
 in the second sleep mode, the oscillator circuit is disabled; and 
 in the third standby mode, the amplifier is biased to a voltage close to its amplifier operating voltage but the oscillator circuit does not generate the periodic signal. 
   
     
     
       22. The clock generation circuit of claim 21 wherein the oscillator circuit is an RC oscillator circuit and the amplifier is included in the RC oscillator circuit. 
     
     
       23. The clock generation circuit of claim 22 where the oscillator circuit is a relaxation oscillator circuit comprising a current generation circuit connected to an integration circuit and the amplifier is included in the current generation circuit. 
     
     
       24. The clock generation circuit of claim 23 wherein, in the third standby mode, a first transistor in the current generation circuit is biased to a voltage close to its transistor operating voltage. 
     
     
       25. The clock generation circuit of claim 23 wherein, in the first full power mode the first transistor is connected between a second transistor and a variable resistance unit and in the third standby mode the first transistor is connected between the second transistor and a plurality of diodes and wherein, in both the first full power mode and the third standby mode, the bias circuit provides a low bias current to the amplifier circuit. 
     
     
       26. The clock generation circuit of claim 25 wherein the gate of the second transistor in the current generation circuit is connected in a current mirror arrangement to the gate of a third transistor in the integration circuit of the relaxation oscillator circuit and wherein in the first full power mode, a mirrored current is provided to a capacitor of the relaxation oscillator circuit. 
     
     
       27. The clock generation circuit of claim 21 wherein the indication comprises a clock request and a standby signal. 
     
     
       28. The clock generation circuit of claim 21 further comprising at least one control input to receive a clock request and a standby signal from a control unit. 
     
     
       29. A power management unit comprising a clock generation circuit including:
 an oscillator circuit including an amplifier and operative to selectively generate a periodic signal;   a bias circuit connected to the amplifier; and   an output circuit receiving the periodic signal from the oscillator circuit and operative to output a clock signal;   wherein the clock generation circuit is adapted to operate in one of a first full power mode, a second sleep mode or a third standby mode, dependent on an indication provided for the clock generation circuit; wherein
 in the first full power mode, the oscillator circuit provides the periodic signal to the output circuit and the output circuit generates the clock signal; 
 in the second sleep mode, the oscillator circuit is disabled; and 
 in the third standby mode, the amplifier is biased to an amplifier voltage close to its operating voltage but the oscillator circuit does not generate the periodic signal; and 
   a switch mode power supply circuit;   wherein, in the first full power mode, the switch mode power supply circuit receives the clock signal from the output circuit and provides power to an electronic circuit.   
     
     
       30. The power management unit of claim 29 wherein the oscillator circuit is an RC oscillator circuit and the amplifier is included in the RC oscillator circuit. 
     
     
       31. The power management unit of claim 29 where the oscillator circuit is a relaxation oscillator circuit comprising a current generation circuit connected to an integration circuit and the amplifier is included in the current generation circuit. 
     
     
       32. A wireless modem comprising a clock generation circuit including:
 an oscillator circuit including an amplifier and operative to selectively generate a periodic signal;   a bias circuit connected to the amplifier; and   an output circuit receiving the periodic signal from the oscillator circuit and operative to output a clock signal;   wherein the clock generation circuit is adapted to operate in one of a first full power mode, a second sleep mode or a third standby mode, dependent on an indication provided for the clock generation circuit; wherein
 in the first full power mode, the oscillator circuit provides the periodic signal to the output circuit and the output circuit generates the clock signal; 
 in the second sleep mode, the oscillator circuit is disabled; and 
 in the third standby mode, the amplifier is biased to an amplifier voltage close to its operating voltage but the oscillator circuit does not generate the periodic signal. 
   
     
     
       33. The wireless modem of claim 32 wherein the oscillator circuit is an RC oscillator circuit and the amplifier is included in the RC oscillator circuit. 
     
     
       34. The wireless modem of claim 32 where the oscillator circuit is a relaxation oscillator circuit comprising a current generation circuit connected to an integration circuit and the amplifier is included in the current generation circuit. 
     
     
       35. The wireless modem of claim 32 further comprising at least one of a digital broadband integrated circuit, a radio frequency integrated circuit, and a power amplifier. 
     
     
       36. A wireless communication terminal comprising a clock generation circuit including:
 an oscillator circuit including an amplifier and operative to selectively generate a periodic signal;   a bias circuit connected to the amplifier; and   an output circuit receiving the periodic signal from the oscillator circuit and operative to output a clock signal;   wherein the clock generation circuit is adapted to operate in one of a first full power mode, a second sleep mode or a third standby mode, dependent on an indication provided for the clock generation circuit; wherein
 in the first full power mode, the oscillator circuit provides the periodic signal to the output circuit and the output circuit generates the clock signal; 
 in the second sleep mode, the oscillator circuit is disabled; and 
 in the third standby mode, the amplifier is biased to an amplifier voltage close to its operating voltage but the oscillator circuit does not generate the periodic signal. 
   
     
     
       37. The wireless communication terminal of claim 36 wherein the oscillator circuit is an RC oscillator circuit and the amplifier is included in the RC oscillator circuit. 
     
     
       38. The wireless communication terminal of claim 36 where the oscillator circuit is a relaxation oscillator circuit comprising a current generation circuit connected to an integration circuit and the amplifier is included in the current generation circuit.