Data control circuit

Abstract

A data control circuit includes an output stage circuit, a switch circuit, and an impedance module. The output stage circuit outputs a data signal. An input terminal of the switch circuit is coupled to an output terminal of the output stage circuit, and an output terminal of the switch circuit is coupled to a post-stage circuit. According to a control of a control signal, the switch circuit determines whether to transmit the data signal of the output stage circuit to the post-stage circuit. The impedance module is configured in the output stage circuit, configured between the output stage circuit and the switch circuit, or configured in the switch circuit. Here, the impedance module reduces noise flowing from the switch circuit to the output stage circuit.

What is claimed is: 
     
       1. A data control circuit comprising:
 an output stage circuit outputting a data signal, wherein the output stage circuit comprises a first n-type transistor and a first p-type transistor, a source terminal of the first n-type transistor being coupled to a ground voltage, a gate terminal of the first n-type transistor being coupled to an input terminal of the output stage circuit, a gate terminal of the first p-type transistor being coupled to the gate terminal of the first n-type transistor, a drain terminal of the first p-type transistor being coupled to an output terminal of the output stage circuit, a source terminal of the first p-type transistor being coupled to a system voltage; 
 a switch circuit, an input terminal of the switch circuit being coupled to an the output terminal of the output stage circuit, an output terminal of the switch circuit being coupled to a post-stage circuit, wherein the switch circuit determines whether to transmit the data signal of the output stage circuit to the post-stage circuit according to a control signal; and 
 an impedance module configured disposed in the output stage circuit for reducing noise flowing from the switch circuit to the output stage circuit, wherein when the impedance module is formed by a transistor, the transistor has a first terminal coupled to a drain terminal of the first n-type transistor, a second terminal coupled to the output terminal of the output stage circuit, and a gate terminal coupled to a fixed voltage turning on the transistor. 
 
     
     
       2. The data control circuit as recited in  claim 1 , wherein the output stage circuit further comprises:
 an inverter circuit, an input terminal of the inverter circuit being coupled to the output terminal of the output stage circuit, an output terminal of the inverter circuit being coupled to the input terminal of the output stage circuit. 
 
     
     
       3. The data control circuit as recited in  claim 2 , wherein the inverter circuit comprises:
 a second p-type transistor, a source terminal of the second p-type transistor being coupled to the system voltage, a gate terminal of the second p-type transistor being coupled to the input terminal of the inverter circuit, a drain terminal of the second p-type transistor being coupled to the output terminal of the inverter circuit; and 
 a second n-type transistor, a drain terminal of the second n-type transistor being coupled to the drain terminal of the second p-type transistor, a source terminal of the second n-type transistor being coupled to the ground voltage, a gate terminal of the second n-type transistor being coupled to the input terminal of the inverter circuit. 
 
     
     
       4. The data control circuit as recited in  claim 2 , wherein the inverter circuit comprises:
 a second p-type transistor, a source terminal of the second p-type transistor being coupled to the system voltage, a gate terminal of the second p-type transistor being coupled to the input terminal of the inverter circuit; 
 a third p-type transistor, a source terminal of the third p-type transistor being coupled to a drain terminal of the second p-type transistor, a drain terminal of the third p-type transistor being coupled to the output terminal of the inverter circuit, a gate terminal of the third p-type transistor being controlled by a clock signal; 
 a second n-type transistor, a drain terminal of the second n-type transistor being coupled to the drain terminal of the third p-type transistor, a gate terminal of the second n-type transistor being controlled by an inverting signal of the clock signal; and 
 a third n-type transistor, a drain terminal of the third n-type transistor being coupled to a source terminal of the second n-type transistor, a source terminal of the third n-type transistor being coupled to the ground voltage, a gate terminal of the third n-type transistor being coupled to the input terminal of the inverter circuit. 
 
     
     
       5. The data control circuit as recited in  claim 1 , wherein the switch circuit comprises:
 a second n-type transistor, a source terminal of the second n-type transistor being coupled to the output terminal of the switch circuit, a drain terminal of the second n-type transistor being coupled to the input terminal of the switch circuit, a gate terminal of the second n-type transistor being controlled by the control signal. 
 
     
     
       6. The data control circuit as recited in  claim 5 , wherein the switch circuit further comprises:
 a second p-type transistor, a source terminal of the second p-type transistor being coupled to the input terminal of the switch circuit, a drain terminal of the second p-type transistor being coupled to the output terminal of the switch circuit, a gate terminal of the second p-type transistor being controlled by an inverting signal of the control signal. 
 
     
     
       7. The data control circuit as recited in  claim 1 , wherein the switch circuit comprises:
 a second p-type transistor, a source terminal of the second p-type transistor being coupled to the input terminal of the switch circuit, a drain terminal of the second p-type transistor being coupled to the output terminal of the switch circuit, a gate terminal of the second p-type transistor being controlled by the control signal. 
 
     
     
       8. The data control circuit as recited in  claim 1 , wherein the impedance module is at least one resistor, an n-type transistor, or a p-type transistor. 
     
     
       9. The data control circuit as recited in  claim 1 , wherein the impedance module just has the first terminal and the second terminal without connection to the gate terminal of the first n-type transistor. 
     
     
       10. A data control circuit comprising:
 an output stage circuit, disposed in a first conductivity type substrate, and configured to output a data signal, wherein the output stage circuit comprises a first inverter circuit, an input terminal of the first inverter circuit is coupled to an input terminal of the output stage circuit, and an output terminal of the first inverter circuit is coupled to an output terminal of the output stage circuit, wherein the first inverter circuit comprises a first n-type transistor and a first p-type transistor, a source terminal of the first n-type transistor is coupled to a ground voltage, a drain terminal of the first n-type transistor is coupled to the output terminal of the output stage circuit, a gate terminal of the first n-type transistor is coupled to the input terminal of the output stage circuit, a gate terminal of the first p-type transistor is coupled to the gate terminal of the first n-type transistor, a drain terminal of the first p-type transistor is coupled to the drain terminal of the first n-type transistor, a source terminal of the first p-type transistor is coupled to a system voltage;   a switch circuit, disposed in the first conductivity type substrate, wherein an input terminal of the switch circuit is coupled to the output terminal of the output stage circuit, an output terminal of the switch circuit is coupled to a post-stage circuit, and the switch circuit is configured to determine whether to transmit the data signal of the output stage circuit to the post-stage circuit according to a control signal, wherein the switch circuit comprises a second n-type transistor and a second p-type transistor, a source terminal of the second n-type transistor is coupled to the output terminal of the switch circuit, a drain terminal of the second n-type transistor is coupled to the input terminal of the switch circuit, a gate terminal of the second n-type transistor is controlled by the control signal, a source terminal of the second p-type transistor is coupled to the input terminal of the switch circuit, a drain terminal of the second p-type transistor is coupled to the output terminal of the switch circuit; and   an impedance module disposed in the output stage circuit, wherein the impedance module comprises a second conductivity type impedance transistor, one of the first conductivity type and the second conductivity type is n-type and the other is p-type, the impedance transistor is coupled between a second conductivity type transistor in the output stage circuit and the output terminal of the output stage circuit, and a gate terminal of the impedance transistor is coupled to a fixed voltage.   
     
     
       11. The data control circuit as recited in claim 10, wherein the output stage circuit further comprises:
 a second inverter circuit, wherein an input terminal of the second inverter circuit is coupled to the output terminal of the first inverter circuit, and an output terminal of the second inverter circuit is coupled to the input terminal of the first inverter circuit.   
     
     
       12. The data control circuit as recited in claim 11, wherein the second inverter circuit comprises:
 a third p-type transistor, wherein a source terminal of the third p-type transistor is coupled to the system voltage, a gate terminal of the third p-type transistor is coupled to the input terminal of the second inverter circuit, and a drain terminal of the third p-type transistor is coupled to the output terminal of the second inverter circuit; and   a third n-type transistor, wherein a drain terminal of the third n-type transistor is coupled to the drain terminal of the third p-type transistor, a source terminal of the third n-type transistor is coupled to the ground voltage, and a gate terminal of the third n-type transistor is coupled to the input terminal of the second inverter circuit.   
     
     
       13. The data control circuit as recited in claim 12, wherein the second inverter circuit further comprises:
 a fourth p-type transistor, wherein a source terminal of the fourth p-type transistor is coupled to the drain terminal of the third p-type transistor, a drain terminal of the fourth p-type transistor is coupled to the output terminal of the second inverter circuit, and a gate terminal of the fourth p-type transistor is controlled by a clock signal; and   a fourth n-type transistor, wherein a drain terminal of the fourth n-type transistor is coupled to the drain terminal of the fourth p-type transistor, a gate terminal of the fourth n-type transistor is controlled by a inverting clock signal, a source terminal of the fourth n-type transistor is coupled to the drain terminal of the third n-type transistor.