Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device comprises a memory cell region, a peripheral circuit region and a boundary region. In the memory cell region, a concave lower electrode and a foundation layer have a same uppermost surface positioned in a height of H above the plane-A. In the boundary region, one concave lower conductive region and a foundation layer have a same uppermost surface positioned in a height of H above the plane-A.

What is claimed is: 
     
       1. A semiconductor device, comprising:
 a memory cell region; 
 a peripheral circuit region; 
 a boundary region formed in a boundary to extend across substantially all of a lower surface of an isolation insulating film positioned between the memory cell region and the peripheral circuit region; and 
 an interlayer insulating film formed across the peripheral circuit region and in the boundary region, 
 wherein the memory cell region comprises:
 a concave lower electrode formed so as to extend upwardly from below plane-A having level equal to an upper surface of the interlayer insulating film and protruding by a height of H above the plane-A; and 
 a foundation layer having a thickness of H formed at least in part on the plane-A other than the a part thereof taken up by the lower electrode, 
 
 wherein the boundary region comprises:
 one concave lower conductive region formed so as to extend upwardly from below plane-A having level equal to the upper surface of the interlayer insulating film and protruding by a height of H above the plane-A; and   the foundation layer having a thickness of H formed on the upper surface of the interlayer insulating film in the boundary region other than a part thereof taken up by the one concave lower conductive region, and   
 wherein the memory cell region and the boundary region comprise:
 a dielectric film formed so as to cover surfaces of the lower electrode, the lower conductive region and the foundation layer; and   an upper conductive region including a conductive layer formed so as to have contact with an uppermost surface of a portion of the dielectric film over the plane-A and the interlayer insulating film, and a convex portion branching off from the conductive layer and disposed facing to the lower electrode and the lower conductive region with an intervention of the dielectric film therebetween; and   
 wherein the interlayer insulating film is adjacent to and in contact with the foundation layer in a portion of the boundary region between the lower conductive region and the peripheral circuit region, and the interlayer insulating film is removed from contact with the foundation layer in the memory cell region. 
 
     
     
       2. The semiconductor device according to  claim 1 ,
 wherein in the memory cell region, the concave lower electrode, the dielectric film covering the concave lower electrode, and the convex portion of the upper conductive region constitute a capacitor. 
 
     
     
       3. The semiconductor device according to  claim 2 ,
 wherein the memory cell region includes at least two capacitors adjacent to each other, and further includes at least two field-effect transistors sharing a first impurity-diffused region and comprising independent second impurity-diffused regions, and 
 each of the second impurity-diffused regions of the field-effect transistors is electrically connected to the capacitor through a first contact plug. 
 
     
     
       4. The semiconductor device according to  claim 1 ,
 wherein the boundary region further comprises a second contact plug electrically connected to the conductive layer of the upper conductive region, 
 the peripheral circuit region further comprises:
 a field-effect transistor; and 
 two third contact plugs electrically connected to a third impurity-diffused region and a fourth impurity-diffused region of the field-effect transistor, and 
 the second contact plug and at least one of the third contact plugs are electrically connected to each other through an interconnect layer. 
 
 
     
     
       5. The semiconductor device according to  claim 1 ,
 wherein the H is 50 nm to 200 nm. 
 
     
     
       6. The semiconductor device according to  claim 1 ,
 wherein a height of the lower electrode is 0.5 μm to 4 μm. 
 
     
     
       7. A semiconductor device, comprising:
 a memory cell region comprising:
 a first capacitor with a crown structure; 
 a second capacitor with a crown structure having the same uppermost surface as the first capacitor; and 
 a first foundation layer formed between the first capacitor and the second capacitor so as to have the same uppermost surface as the first and second capacitors, 
 a peripheral circuit region formed surrounding the memory cell region, and 
 
 a boundary region formed to extend across substantially all of a lower surface of an isolation insulating film positioned between the memory cell region and the peripheral circuit region, comprising:
 a dummy capacitor disposed so as to surround the memory cell region, and formed so as to have the same uppermost surface as the first and second capacitors; and 
 a second foundation layer formed on an upper surface of an interlayer insulating film in the boundary region and between the capacitor positioned in a boundary region side among the first and the second capacitors and the dummy capacitor and to substantially cover the boundary region other than a part thereof taken up by the dummy capacitor, so as to have the same uppermost level as the first and second capacitors; 
 
 wherein the interlayer insulating film is formed across the peripheral circuit region, and is formed in the boundary region adjacent and in contact with the second foundation layer, and is removed from contact with the first foundation layer in the memory cell region. 
 
     
     
       8. The semiconductor device according to  claim 7 ,
 wherein the memory cell region further comprises: 
 a third capacitor with a crown structure; 
 two field-effect transistors sharing a first impurity-diffused region and comprising independent second impurity-diffused regions; and 
 a first contact plug electrically connecting each of the second impurity-diffused regions of the field-effect transistors with the second and the third capacitors. 
 
     
     
       9. The semiconductor device according to  claim 7 ,
 wherein the boundary region further comprises a second contact plug electrically connected to the dummy capacitor, 
 the peripheral circuit region further comprises:
 a field-effect transistor; and 
 two third contact plugs electrically connected to a third impurity-diffused region and a fourth impurity-diffused region of the field-effect transistor, and 
 the second contact plug and at least one of the third contact plugs are electrically connected to each other through an interconnect layer. 
 
 
     
     
       10. The semiconductor device according to  claim 7 ,
 wherein a thickness of the first and the second foundation layers is 50 nm to 200 nm. 
 
     
     
       11. The semiconductor device according to  claim 7 , wherein a height of the dummy capacitor is 0.5 μm to 4 μm. 
     
     
       12. A semiconductor device comprising:
 a memory cell region; 
 a peripheral region; and 
 a boundary region encircled between the memory cell region and the peripheral region, 
 the memory cell region including:
 a plurality of cell capacitors; and 
 a foundation layer coupling the cell capacitors to one another at an uppermost upper portion of lower electrodes of the cell capacitors and, the foundation layer including a plurality of holes, the foundation layer being elongated to form an elongated portion over to substantially cover the boundary region; 
 
 wherein an interlayer insulating film is formed across the peripheral circuit region, is formed adjacent and in contact with the elongated portion of the foundation layer in the boundary region, and is removed from contact with the foundation layer in the memory cell region. 
 
     
     
       13. The semiconductor device according to  claim 12 ,
 wherein the boundary region comprises a dummy capacitor, the dummy capacitor being coupled to the cell capacitors via the elongated portion of the foundation layer. 
 
     
     
       14. The semiconductor device according to  claim 12 ,
 wherein the memory cell region further includes: 
 at least two cell capacitors adjacent to each other; 
 two field-effect transistors sharing a first impurity diffused region and comprising independent second impurity diffused regions; and 
 a first contact plug electrically connecting each of the second impurity-diffused regions of the field-effect transistors with the cell capacitors. 
 
     
     
       15. The semiconductor device according to  claim 13 ,
 wherein the boundary region further comprises a second contact plug electrically connected to the dummy capacitor, 
 the peripheral circuit region comprises:
 a field-effect transistor; and 
 two third contact plugs electrically connected to a third impurity-diffused region and a fourth impurity-diffused region of the field-effect transistor, and the second contact plug and at least one of the third contact plugs are electrically connected to each other through an interconnect layer. 
 
 
     
     
       16. The semiconductor device according to  claim 12 , wherein the thickness of the foundation layer is 50 nm to 200 nm. 
     
     
       17. The semiconductor device according to  claim 13 , wherein a height of the dummy capacitor is 0.5 μm to 4 μm. 
     
     
       18. The semiconductor device according to claim 12, wherein an end of the foundation layer substantially coincides with the boundary region. 
     
     
       19. A semiconductor device comprising:
 a memory cell region;   a peripheral circuit region; and   a boundary region formed between the memory cell region and the peripheral circuit region;   wherein the boundary region comprises:
 a ring-shaped lower conductive region surrounding the memory cell region; 
   the ring-shaped lower conductive region having a first outer wall facing the cell region, and a second outer wall facing the peripheral circuit region;   wherein the peripheral circuit region and the boundary region comprises:   an interlayer insulating film having an upper surface thereof formed across the peripheral circuit region, and is in contact with and extending from the second outer wall;   wherein the memory cell region comprises:   a plurality of lower electrodes extending upwardly and protruding above a level of the upper surface of the interlayer insulating film; and   a foundation layer having openings thereon and formed in the memory cell region to connect upper portions of individual ones of said lower electrodes;   wherein the foundation layer is free from the peripheral circuit region, and the interlayer insulating film is free from contacting the foundation layer in the memory cell region; and   wherein the memory cell region and the boundary region comprises:   the foundation layer extending from the memory cell region to the first outer wall;   a dielectric film formed to cover an inner surface and an outer surface of the lower electrodes, the first outer wall of the ring-shaped lower conductive region, and a surface of the foundation layer; and   a conductive upper electrode layer formed on a surface of the dielectric film.   
     
     
       20. The semiconductor device according to claim 19, the ring-shaped lower conductive region is in concave shape. 
     
     
       21. The semiconductor device according to claim 20, the plurality of lower electrodes are in cylindrical shape. 
     
     
       22. The semiconductor device according to claim 21, the ring-shaped lower conductive region and the lower electrodes are formed with a same material and have a same height. 
     
     
       23. The semiconductor device according to claim 20, wherein the boundary region includes only one ring-shaped lower conductive region. 
     
     
       24. The semiconductor device according to claim 19,
 wherein in the memory cell region, the lower electrode, the dielectric film covering the lower electrodes, and the conductive upper electrode constitute a capacitor.   
     
     
       25. The semiconductor device according to claim 24,
 wherein the memory cell region includes at least two capacitors adjacent to each other, and further includes at least two field-effect transistors sharing a first impurity-diffused region and comprising independent second impurity-diffused regions, and   each of the second impurity-diffused regions of the field-effect transistors is electrically connected to the capacitor through a first contact plug.   
     
     
       26. The semiconductor device according to claim 19,
 wherein the boundary region further comprises a second contact plug electrically connected to the conductive upper electrode layer,   the peripheral circuit region further comprises:   a field-effect transistor having source/drain regions disposed at both sides of a gate electrode; and   the second contact plug and one source/drain region are electrically connected to each other through an interconnect layer.   
     
     
       27. The semiconductor device according to claim 19,
 wherein the foundation layer has a thickness of 50 nm to 200 nm.   
     
     
       28. The semiconductor device according to claim 19, wherein a height of the lower electrodes is 0.5 μm to 4 μm.