Storage medium and semiconductor package

Abstract

A semiconductor package includes a semiconductor chip formed with a non-volatile semiconductor memory, a resin encapsulation that encapsulates the semiconductor chip, electrodes in a lattice (solder balls) formed and arrayed in a lattice on a bottom surface of the resin encapsulation. The solder balls include a signal electrode formed within the central region of the array and a dummy electrode formed outside the signal electrode.

What is claimed is: 
     
       1. A storage medium comprising:
 a semiconductor package having a semiconductor chip, a resin encapsulation that encapsulates the semiconductor chip, and a plurality of electrodes arrayed on a bottom surface of the resin encapsulation; and   a substrate including a conductor that joins the electrodes, and having the semiconductor package mounted thereon, wherein   the electrodes include a plurality of signal electrodes formed within a central region of the array, and a plurality of dummy electrodes formed in an outer region of the signal electrodes,   each of the signal electrodes includes a first pad as a projection-electrode forming pad for a power supply line or a signal line, and a first projection electrode formed on the first pad, and   each of the dummy electrodes includes a second pad as a projection-electrode forming pad for a dummy electrode and a second projection electrode formed on the second pad.   
     
     
       2. The storage medium according to  claim 1 , wherein only the dummy electrodes among the signal electrodes and the dummy electrodes are disposed in the outer region. 
     
     
       3. The storage medium according to  claim 1 , wherein the dummy electrode further includes a third pad for burying a vacant region, and no projection electrode is formed on the third pad. 
     
     
       4. The storage medium according to  claim 1 , wherein the central region in which the signal electrodes are formed has a region of a width about ⅓ to ½ of entire width of the array. 
     
     
       5. The storage medium according to  claim 1 , wherein a proportion in number of the signal electrodes to the electrodes is less than 30%. 
     
     
       6. The storage medium according to  claim 1 , wherein a proportion in number of the signal electrodes to the electrodes is less than 20%. 
     
     
       7. The storage medium according to  claim 1 , wherein the signal electrodes are placed to exhibit line symmetry about a center line of the array formed by the electrodes or point symmetry about a center of the array. 
     
     
       8. The storage medium according to  claim 1 , wherein the dummy electrodes are formed to enclose entire circumference of the signal electrodes. 
     
     
       9. The storage medium according to  claim 1 , wherein semiconductor chips are stacked and encapsulated in the resin encapsulation. 
     
     
       10. The storage medium according to  claim 1 , wherein the semiconductor chip has a NAND flash memory incorporated therein. 
     
     
       11. A semiconductor package comprising:
 a semiconductor chip;   a wiring substrate having the semiconductor chip mounted on a first surface; and   a plurality of projection electrodes formed on a second surface opposite to the first surface of the wiring substrate, wherein   a bonding pad, to which a bonding wire extending from the semiconductor chip is connected, is formed at an edge of the first surface on the wiring substrate, and a plurality of projection-electrode forming pads for forming the projection electrodes are arrayed and formed in a lattice on the second surface, and   the projection-electrode forming pads include first projection-electrode forming pads as projection-electrode forming pads for a power supply line formed within a central region of the array and second projection-electrode forming pads as projection-electrode forming pads for a dummy electrode formed in an outer region of the central region,   the projection electrodes include first projection electrodes formed on the first projection-electrode forming pads and second projection electrodes formed on the second projection-electrode forming pads,   two or more second projection-electrode forming pads among the second projection-electrode forming pads are connected to one another by a connection pattern formed on the second surface, and   the first projection-electrode forming pads are connected to the bonding pad through the plurality of second projection-electrode forming pads connected by the connection pattern, and a through hole formed in the wiring substrate.   
     
     
       12. The semiconductor package according to  claim 11 , wherein in the second projection-electrode forming pads connected by the connection pattern, the second projection-electrode forming pads adjacent to each other are connected. 
     
     
       13. The semiconductor package according to  claim 11 , wherein only the second projection-electrode forming pads are disposed in the outer region. 
     
     
       14. The semiconductor package according to  claim 11 , wherein the wiring substrate forms a rectangle, and the bonding pad is arranged at an edge on a short side of the wiring substrate. 
     
     
       15. The semiconductor package according to  claim 11 , wherein the semiconductor chips are stacked and mounted on the wiring substrate. 
     
     
       16. A storage device comprising:
 a semiconductor package including a plurality of semiconductor chips, a substrate, a resin encapsulation that encapsulates the plurality of semiconductor chips, and an array of electrodes on a bottom surface of the substrate, the plurality of semiconductor chips being mounted on the substrate; wherein   the electrodes include a plurality of signal electrodes formed within a central region of the array, a plurality of dummy electrodes formed on an outer region outside of the central region, and a proportion of a number of the signal electrodes to a total number of the electrodes is 10-30%,   the signal electrodes include a first pad as a projection-electrode forming pad for a power supply line or a signal line, and a first projection electrode formed on the first pad, and   the dummy electrodes include a second pad as a projection-electrode forming pad for a dummy electrode and a second projection electrode formed on the second pad.   
     
     
       17. The storage device according to claim 16, wherein
 the outer region includes a first region and a second region, the first region including the dummy electrodes surrounding the central region and including four corners, the second region including one or more lines of the dummy electrodes formed outside of the four corners of the first region.   
     
     
       18. The storage device according to claim 16, wherein only the dummy electrodes among the signal electrodes and the dummy electrodes are disposed in the outer region. 
     
     
       19. The storage device according to claim 16, wherein at least one of the dummy electrodes further includes a third pad for burying a vacant region, and no projection electrode is formed on the third pad. 
     
     
       20. The storage device according to claim 16, wherein the central region in which the signal electrodes are formed has a region of a width about ⅓ to ½ of an entire width of the array. 
     
     
       21. The storage device according to claim 16, wherein a proportion in number of the signal electrodes to the electrodes is less than 20%. 
     
     
       22. The storage device according to claim 16, wherein the signal electrodes are placed to exhibit line symmetry about a center line of the array formed by the electrodes or point symmetry about a center of the array. 
     
     
       23. The storage device according to claim 16, wherein the dummy electrodes are formed to enclose an entire circumference of the signal electrodes. 
     
     
       24. The storage device according to claim 16, wherein the semiconductor chips are stacked and encapsulated in the resin encapsulation. 
     
     
       25. The storage device according to claim 24, the substrate comprises a wiring substrate, wherein
 the wiring substrate and a plurality of bonding wires are encapsulated in the resin encapsulation,   the bonding wires are electrically connected to the semiconductor chips and the wiring substrate,   the bonding wires extending from the semiconductor chips are connected to a wiring pattern at an end of the wiring substrate, and   the semiconductor chips are stacked in a slightly deviating manner in the resin encapsulation.   
     
     
       26. The storage device according to claim 25, wherein
 the semiconductor chips are stacked to be deviated by a predetermined amount such that top surfaces of peripheries of the semiconductor chips to which the bonding wires are connected are not overlapped by another one of the semiconductor chips, and   one of the bonding wires is connected to one side of each of the semiconductor chips.   
     
     
       27. The storage device according to claim 25, wherein
 the electrodes form a line in a long-side direction of the array and a line in a short-side direction of the array, and   the electrodes are arrayed in an approximate rectangular shape that has a center matching that of the wiring substrate.   
     
     
       28. The storage device according to claim 25, further comprising:
 bonding pads arranged on a short side of the wiring substrate, and   through holes in the wiring substrate are connected by patterns on the wiring substrate.   
     
     
       29. The storage device according to claim 25, wherein the first pads are electrically connected to at least one of the semiconductor chips by a through hole and a pattern on the wiring substrate. 
     
     
       30. The storage device according to claim 16, wherein at least one of the semiconductor chips has a NAND flash memory incorporated therein. 
     
     
       31. The storage device according to claim 16, wherein
 the semiconductor package is 14×18 mm in outer dimension, and   the semiconductor package is a maximum of 1.46 millimeters in height.   
     
     
       32. The storage device according to claim 16, wherein
 the central region has a width about ⅓ of an entire width in a long-side direction of the array,   the signal electrodes and a subset of the dummy electrodes are in the central region, and   the remaining dummy electrodes are spread out in the outer region in at least one long-side direction from the central region.   
     
     
       33. The storage device according to claim 16, wherein
 the outer region is located on both sides of the central region, and   the dummy electrodes are formed in an array to almost occupy at least one of the sides of the outer region.   
     
     
       34. The storage device according to claim 16, wherein
 the dummy electrodes are formed in two lines in a short-side direction of the array on the outer region, and   each of the lines includes at least three projection-electrodes.   
     
     
       35. The storage device according to claim 34, wherein
 the signal electrodes include Vcc electrodes;   the Vcc electrodes are formed in a Vcc electrode line in the short-side direction, and   the Vcc electrode line is next to the two dummy electrode lines.   
     
     
       36. The storage device according to claim 16, wherein
 three dummy electrodes are formed in the outer region, and   at least a Vcc electrode in the central region form a line in a long-side direction of the array.   
     
     
       37. The storage device according to claim 16, wherein at least one of the semiconductor chips includes a plurality of memory cells, the memory cells being capable of multiple-valued recording. 
     
     
       38. A storage system comprising:
 a semiconductor package having a plurality of semiconductor chips, a first substrate, a resin encapsulation encapsulating the plurality of semiconductor chips, and an array of electrodes on a bottom surface of the first substrate; and   a second substrate; wherein   the semiconductor package is mounted on the second substrate,   the electrodes include a plurality of signal electrodes on a central region of the bottom surface, and a plurality of dummy electrodes on an outer region outside of the central region,   a proportion of a number of the signal electrodes to a total number of the plurality of electrodes is 10-30%,   the signal electrodes include a first pad as a projection-electrode forming pad for a power supply line or a signal line, and a first projection electrode formed on the first pad, and   the dummy electrodes include a second pad as a projection-electrode forming pad for a dummy electrode and a second projection electrode formed on the second pad.   
     
     
       39. The storage system according to claim 38, wherein
 the outer region includes a first region and a second region, the first region including the dummy electrodes surrounding the central region and including four corners, the second region including one or more lines of the dummy electrodes formed outside of the four corners of the first region.   
     
     
       40. The storage system according to claim 38, wherein the second substrate includes a plurality of conductors, the plurality of conductors including first conductors and second conductors, the first conductors being in contact with the first projection electrodes, the second conductors being in contact with the second projection electrodes. 
     
     
       41. The storage system according to claim 38, wherein at least one of the dummy electrodes further includes a third pad for burying a vacant region, and no projection-electrode is formed on the third pad. 
     
     
       42. The storage system according to claim 38, wherein the central region in which the signal electrodes are formed has a width about ⅓ to ½ of an entire width of the array. 
     
     
       43. The storage system according to claim 38, wherein a proportion in number of the signal electrodes to the electrodes is less than 20%. 
     
     
       44. The storage system according to claim 38, wherein the signal electrodes are placed to exhibit line symmetry about a center line of the array formed by the electrodes or point symmetry about a center of the array. 
     
     
       45. The storage system according to claim 38, wherein the dummy electrodes are arrayed to at least one side of an entire circumference of the signal electrodes. 
     
     
       46. The storage system according to claim 38, wherein the semiconductor chips are stacked and encapsulated in the resin encapsulation. 
     
     
       47. The storage system according to claim 46, wherein
 a plurality of bonding wires are encapsulated in the resin encapsulation,   the bonding wires are electrically connected to the semiconductor chips and the first substrate,   the bonding wires extending from the semiconductor chips are connected to a wiring pattern at an end of the first substrate, and   the semiconductor chips are stacked in a slightly deviating manner in the resin encapsulation.   
     
     
       48. The storage system according to claim 47, wherein
 the semiconductor chips are stacked to be deviated by a predetermined amount such that top surfaces of peripheries of the semiconductor chips to which the bonding wires are connected are not overlapped by another one of the semiconductor chips, and   one of the bonding wires is connected to one side of each of the semiconductor chips.   
     
     
       49. The storage system according to claim 38, wherein at least one of the semiconductor chips has a NAND flash memory incorporated therein. 
     
     
       50. The storage system according to claim 38, further comprising
 a controller mounted on the second substrate, and   a power supply circuit mounted on the second substrate, wherein   the plurality of semiconductor chips include a first semiconductor chip and a second semiconductor chip, the first semiconductor chip and the second semiconductor chip are partially overlapped, and a peripheral portion of the second semiconductor chip is not overlapped on one side of the first semiconductor chip.   
     
     
       51. The storage system according to claim 38, wherein
 the semiconductor package is 14×18 mm in outer dimension, and   the semiconductor package is a maximum of 1.46 millimeters in height from the second substrate.   
     
     
       52. The storage system according to claim 38, wherein
 the electrodes form a line in a long-side direction of the array and a line in a short-side direction of the array, and   the electrodes are arrayed in an approximate rectangular shape that has a center matching that of the first substrate.   
     
     
       53. The storage system according to claim 38, wherein
 the central region has a width about ⅓ of an entire width in a long-side direction of the array,   the signal electrodes and a subset of the dummy electrodes are in the central region, and   the remaining dummy electrodes are spread out in the outer region in at least one long-side direction from the central region.   
     
     
       54. The storage system according to claim 38, wherein
 the outer region is located on both sides of the central region, and   the dummy electrodes are formed in an array to almost occupy at least one of the sides of the outer region.   
     
     
       55. The storage system according to claim 38, wherein
 the dummy electrodes are formed in two lines in a short-side direction of the array on the outer region, and   each of the lines includes at least three projection-electrodes.   
     
     
       56. The storage system according to claim 55, wherein
 Vcc electrodes in the central region are formed in a Vcc electrode line in the short-side direction of the array, and   the Vcc electrode line is next to the two dummy electrode lines.   
     
     
       57. The storage system according to claim 38, further comprising:
 bonding pads arranged on a short side of the first substrate, and   through holes in the first substrate that are connected by patterns on the first substrate.   
     
     
       58. The storage system according to claim 38, wherein the first pads are electrically connected to at least one of the semiconductor chips by a through hole and a pattern on the first substrate. 
     
     
       59. The storage system according to claim 38, wherein
 the signal electrodes include a Vcc electrode,   three dummy electrodes are formed in the outer region, and   the Vcc electrode and the three dummy electrodes form a line in a long-side direction of the array.   
     
     
       60. The storage system according to claim 38, further comprising a controller,
 wherein the controller controls at least one of the semiconductor chips in the semiconductor package, the at least one of the semiconductor chips includes a NAND flash memory.   
     
     
       61. The storage system according to claim 60, further comprising a volatile memory mounted on the second substrate. 
     
     
       62. The storage system according to claim 61, wherein the volatile memory is Dynamic Random Access Memory. 
     
     
       63. The storage system according to claim 61, wherein a power supply circuit is incorporated in a second semiconductor package. 
     
     
       64. The storage system according to claim 63, wherein an underfill agent is filled between the second substrate and the second semiconductor package. 
     
     
       65. The storage system according to claim 60, further comprising third semiconductor packages mounted on the second substrate, the third semiconductor packages including NAND flash memories. 
     
     
       66. The storage system according to claim 65, wherein the number of the third semiconductor packages is four or more. 
     
     
       67. The storage system according to claim 65, wherein a plurality of semiconductor chips are stacked in each of the third semiconductor packages. 
     
     
       68. The storage system according to claim 38, wherein a connector is arranged at an outer periphery of the second substrate. 
     
     
       69. The storage system according to claim 38, wherein at least one of the semiconductor chips includes a plurality of memory cells, the memory cells being capable of multiple-valued recording. 
     
     
       70. The storage system according to claim 38, wherein the central region in which the signal electrodes are formed has a region of a width about ⅓ to ½ of an entire width of the array. 
     
     
       71. The storage system according to claim 38, wherein an outer dimension of the second substrate is substantially the same in size as that of a 1.8-inch HDD according to the HDD standard. 
     
     
       72. A storage system comprising:
 a mounting substrate; and   a plurality of semiconductor packages mounted on the mounting substrate;   wherein   at least one of the semiconductor packages includes:   a plurality of semiconductor chips;   a wiring substrate on which the plurality of semiconductor chips are mounted on a first surface; and   a plurality of projection electrodes formed on a second surface opposite to the first surface of the wiring substrate, wherein   a plurality of projection-electrode forming pads for forming the projection electrodes are arrayed on the second surface,   the projection-electrode forming pads include first projection-electrode forming pads as projection-electrode forming pads formed within a central region of the array for at least a power supply line and second projection-electrode forming pads as projection-electrode forming pads for a dummy electrode formed on an outer region outside of the central region,   a proportion of a number of the first projection-electrode forming pads in the central region to a total number of the first and second projection-electrode forming pads is 10-30 percent,   the projection electrodes include first projection electrodes formed on the first projection-electrode forming pads and second projection electrodes formed on the second projection-electrode forming pads.   
     
     
       73. The storage system according to claim 72, wherein
 the outer region includes a first region and a second region, the first region including the dummy electrodes surrounding the central region and including four corners, the second region including one or more lines of the dummy electrodes formed outside of the four corners of the first region.   
     
     
       74. The storage system according to claim 72, wherein the mounting substrate includes a plurality of conductors, the plurality of conductors including first conductors and second conductors, the first conductors being in contact with the first projection electrodes, the second conductors being in contact with the second projection electrodes. 
     
     
       75. The storage system according to claim 72, further comprising
 a power supply circuit mounted on the mounting substrate; and   a controller mounted on the mounting substrate, wherein   the plurality of semiconductor chips include a first semiconductor chip and a second semiconductor chip, the first semiconductor chip and the second semiconductor chip are partially overlapped, and a peripheral portion of the second semiconductor chip is not overlapped on one side of the first semiconductor chip, and   a bonding pad, to which a bonding wire extending from at least one of the semiconductor chips is connected, is formed at an edge of the first surface of the wiring substrate.   
     
     
       76. The storage system according to claim 72, wherein the central region in which the signal electrodes are formed has a region of a width about ⅓ to ½ of an entire width of the array. 
     
     
       77. The storage system according to claim 72, wherein an outer dimension of the mounting substrate is substantially the same in size as that of a 1.8-inch HDD according to the HDD standard. 
     
     
       78. A storage device comprising:
 a substrate, and   a semiconductor package including a semiconductor chip and an array of electrodes on a bottom surface of the semiconductor package, the semiconductor package being mounted on the substrate, the electrodes including a plurality of signal electrodes formed within a central region of the bottom surface of the semiconductor package, and a plurality of dummy electrodes formed on an outer region outside of the central region,   wherein a proportion of a number of the signal electrodes to a total number of the plurality of electrodes is 10-30 percent.   
     
     
       79. The storage device according to claim 78, wherein the central region in which the signal electrodes are formed has a region of a width about ⅓ to ½ of an entire width of the array. 
     
     
       80. A storage device comprising:
 a semiconductor package including a semiconductor chip, a substrate, and an array of electrodes on a bottom surface of the substrate, the semiconductor package being mounted on the substrate; wherein   the electrodes include a plurality of dummy electrodes formed in a rectangular outer region and a plurality of signal electrodes formed within a substantially square central region disposed within the outer region, and the substantially square central region being rotated by 45 degrees with respect to the rectangular outer region,   the signal electrodes include a first projection electrode, and   the dummy electrodes include a second projection electrode.   
     
     
       81. The storage device according to claim 80, wherein a proportion of a number of the signal electrodes to a total number of the plurality of electrodes is 10-30%. 
     
     
       82. The storage device according to claim 81, wherein a proportion in number of the signal electrodes to the electrodes is less than 20%. 
     
     
       83. The storage device according to claim 80, wherein the central region in which the signal electrodes are formed has a region of a width about ⅓ to ½ of an entire width of the array. 
     
     
       84. A storage device comprising:
 a substrate, and   a semiconductor package including a semiconductor chip and an array of electrodes on a bottom surface of the semiconductor package, the semiconductor package being mounted on the substrate, the electrodes including a plurality of signal electrodes formed within a central region of the bottom surface of the semiconductor package, and a plurality of dummy electrodes formed on an outer region outside of the central region,   wherein the central region in which the signal electrodes are formed has a region of a width about ⅓ to ½ of an entire width of the array.   
     
     
       85. The storage device according to claim 84, wherein all of the of signal electrodes are formed within the central region.