Digital-to-time converter

Abstract

A digital-to-time converter includes a first node, a second node configured to receive a reference signal, and a digital-to-analog signal converter configured to couple a passive impedance to the first node. The passive impedance is selected according to the digital code. The digital-to-time converter also includes a first switch configured to selectively couple the first node to a second reference signal in response to the input signal and a comparator configured to generate the output signal based on a first signal on the first node and the reference signal on the second node. The digital-to-time converter may include a second switch configured to selectively couple the first node to a third reference signal in response to a first control signal.

What is claimed is: 
     
       1. An apparatus comprising:
 a digital-to-time converter comprising:
 a first node; 
 a second node configured to receive a reference signal; 
 a digital-to-analog signal converter configured to couple a passive impedance to the first node, the passive impedance being selected according to a digital code; 
 a first switch configured to selectively couple the first node to a second reference signal in response to an input signal; and 
 a comparator configured to generate the an output signal based on a comparison of a first signal on the first node and to the reference signal on the second node, 
 
 wherein the digital-to-analog signal converter comprises a plurality of elements configured to receive the digital code, the digital code having a plurality of bits, each of the plurality of elements comprising:
 an inverter configured to receive a corresponding bit of the plurality of bits; and 
 a capacitor coupled in series between the inverter and the first node. 
 
 
     
     
       2. The apparatus, as recited in  claim 1 , wherein edges of the output signal correspond to the input signal edges of the input signal linearly delayed based on the digital code. 
     
     
       3. The apparatus, as recited in  claim 1 , wherein the digital-to-time converter further comprises a second switch configured to selectively couple the first node to a third reference signal in response to a first control signal, the first node being charged to a reset voltage level in response to the first control signal closing the second switch. 
     
     
       4. The apparatus, as recited in  claim 3 , wherein the first node is charged to a pedestal voltage level according to the passive impedance and in response to the first and second switches being open first switch being open and the second switch being open. 
     
     
       5. The apparatus, as recited in  claim 1 , wherein the digital-to-analog signal converter introduces a pedestal voltage to the first node after a reset phase. 
     
     
       6. The apparatus, as recited in  claim 1 ,
 wherein an active phase of a first control signal couples the first node to the second reference signal, causing the first node to charge to a first voltage level; and 
 wherein an active phase of the input signal couples the first node to the reference signal, causing the first node to charge to a second voltage level, the second voltage level being greater than a voltage level on the second node, and the voltage level on the second node being greater than the first voltage level. 
 
     
     
       7. The apparatus, as recited in  claim 1 , wherein the digital-to-analog signal converter comprises:
 a plurality of elements configured to receive the digital code, the digital code having a plurality of bits, each of the plurality of elements comprising:
 an inverter configured to receive a corresponding bit of the plurality of bits; and 
 a capacitor coupled in series between the inverter and the first node. 
   
     
     
       8. The apparatus, as recited in  claim 1  An apparatus comprising:
 a digital-to-time converter comprising:
 a first node; 
 a second node configured to receive a reference signal; 
 a digital-to-analog signal converter configured to couple a passive impedance to the first node, the passive impedance being selected according to a digital code; 
 a first switch configured to selectively couple the first node to a second reference signal in response to an input signal; and 
 a comparator configured to generate an output signal based on a comparison of a first signal on the first node to the reference signal, 
 
 wherein the input signal and the digital code are generated by a frequency divider according to a divide code and a reference clock signal, the input signal being a frequency-divided version of the reference clock signal and the digital code being an associated digital quantization error. 
 
     
     
       9. The apparatus, as recited in  claim 1 , wherein the digital-to-time converter is configured as a subrange data converter with respect to an integer frequency divider configured to generate the input signal and the digital code based on an input clock signal and a digital divider code. 
     
     
       10. The apparatus, as recited in  claim 1 , wherein the digital-to-time converter is configured to sample-and-hold the input signal in a time-to-digital signal converter. 
     
     
       11. The apparatus, as recited in  claim 3 , wherein the digital-to-time converter further comprises a voltage-to-current generator configured to generate the second reference signal, the voltage-to-current generator comprising a switched capacitor switched-capacitor resistor. 
     
     
       12. The apparatus, as recited in  claim 1 , wherein the digital-to-time converter is included in an output path of a clock synthesizer circuit. 
     
     
       13. The apparatus, as recited in  claim 1 , wherein the digital-to-time converter is included in a feedback loop of a phase-locked loop. 
     
     
       14. A method comprising:
 establishing a first voltage level on a first node; 
 generating an input signal and a digital code based on a reference clock signal and a digital divider code; 
 selecting a passive impedance according to the digital code;  
 changing a voltage on the first node from the first voltage level to a second voltage level according to a digital code and at a predetermined slew rate using the passive impedance, a switching threshold voltage level being between the first voltage level and the second voltage level; and 
 generating an output voltage signal based on a comparison of the voltage on the first node to the switching threshold voltage level, the output voltage signal having an edge delayed from a corresponding edge of an the input signal based on the digital code. 
 
     
     
       15. The method, as recited in  claim 14 , wherein establishing the first voltage level comprises selectively coupling the first node to a reset voltage having the first voltage level. 
     
     
       16. The method, as recited in  claim 14 , wherein changing the voltage comprises:
 changing the voltage on the first node from the first voltage level to a second voltage level according to the digital code; and 
 changing the voltage on the first node from the second voltage level to a third voltage level in response to the input signal. 
 
     
     
       17. The method, as recited in  claim 14 , wherein changing the voltage on the first node comprises:
 generating a current by selectively opening and closing a switch coupled to a switched capacitor switched-capacitor resistor at a predetermined frequency. 
 
     
     
       18. The method, as recited in  claim 14 , further comprising:
 generating the input signal and the digital code based on a reference clock signal and a digital divider code.   
     
     
       19. The method, as recited in  claim 14 , further comprising:
 calibrating a gain of a digital-to-time delay conversion based on the output voltage signal and a delayed version of the input signal. 
 
     
     
       20. An apparatus comprising:
 a comparator configured to generate an output signal based on a comparison of a first signal on a first node and to a reference signal on a second node; and 
 means for generating the first signal using a passive impedance selected according to a digital code and having a predetermined slew rate, the first signal having a voltage level based on the passive impedance after a reset phase of a digital-to-time conversion and during a first phase of an input signal, the first signal slewing from the voltage level to a reference voltage level during a second phase of the input signal, the output signal having an edge with an edge delay with respect to a corresponding edge of an the input signal, the edge delay being based on the digital code; and 
 means for generating the input signal and the digital code based on a reference clock signal and a digital divider code. 
 
     
     
       21. The apparatus, as recited in claim 8, wherein the digital-to-analog signal converter comprises:
 a plurality of elements configured to receive the digital code, the digital code having a plurality of bits, each of the plurality of elements comprising: an inverter configured to receive a corresponding bit of the plurality of bits; and a capacitor coupled in series between the inverter and the first node.