Thin film transistor array panel

Abstract

A thin film transistor array panel includes a substrate, a light blocking film disposed on the substrate, a buffer layer covering the light blocking film, and a channel region disposed on the buffer layer. A source region and a drain region are disposed in the same layer as the channel region. A gate insulating layer is disposed on the channel region, and a gate electrode overlaps the channel region, with the gate insulating layer interposed between the gate electrode and the channel region. A passivation layer is disposed on the gate electrode, the source region, the drain region, and the buffer layer. A source electrode and a drain electrode are disposed on the passivation layer, wherein the channel region, the source region, and the drain region comprise an oxide semiconductor, and wherein a carrier concentration of the source region and the drain region is larger than in the channel region.

What is claimed is: 
     
       1. A thin film transistor array panel comprising:
 a substrate; 
 a light blocking film disposed on the substrate; 
 a buffer layer covering the light blocking film and the substrate; 
 a channel region disposed on the buffer layer; 
 a source region and a drain region facing each other with respect to the channel region, the source region and the drain region being disposed in the same layer as the channel region and connected to the channel regionan oxide semiconductor comprising a source region, a drain region, and the channel region; 
 a gate insulating layer disposed on the channel region; 
 a gate electrode overlapping the channel region, the gate insulating layer interposed between the gate electrode and the channel region; 
 a passivation layer disposed on and directly contacted to the gate electrode, the source region, the drain region, and the buffer layer; and 
 a source electrode and a drain electrode disposed on the passivation layer, 
 wherein the channel region, the source region, and the drain region comprise an oxide semiconductor, and 
 wherein a carrier concentration of the source region and the drain region is larger than a carrier concentration of the channel region. 
 
     
     
       2. The thin film transistor array panel of  claim 1 , wherein
 the source region and the drain region comprise a reduced oxide semiconductor.   
     
     
       3. The thin film transistor array panel of claim  2  1, wherein
 the source region and the drain region further comprise at least one selected from fluorine (F), hydrogen (H), and sulfur (S). 
 
     
     
       4. The thin film transistor array panel of  claim 3 , wherein
 a concentration of at least one selected from fluorine (F), hydrogen (H), and sulfur (S) included in the source region and the drain region is equal to or more than about 10 15  units/cm 3 . 
 
     
     
       5. The thin film transistor array panel of  claim 4 , wherein
 the carrier concentration of the channel region is less than about 10 18  units/cm 3 , and the carrier concentration of the source region and the drain region is equal to or more than about 10 18  units/cm 3 . 
 
     
     
       6. The thin film transistor array panel of  claim 5 , wherein
 the source electrode is connected to the source region, and the drain electrode is connected to the drain region. 
 
     
     
       7. The thin film transistor array panel of  claim 5 , wherein
 the gate insulating layer and the gate electrode are disposed on the channel region, and   an edge boundary of the gate electrode, an edge boundary of the gate insulating layer, and an edge boundary of the channel region are substantially aligned with each other.   
     
     
       8. The thin film transistor array panel of claim  1  20, wherein
 the source region and the drain region further comprise at least one selected from fluorine (F), hydrogen (H), and sulfur (S). 
 
     
     
       9. The thin film transistor array panel of  claim 8 , wherein
 a concentration of at least one selected from fluorine (F), hydrogen (H), and sulfur (S) included in the source region and the drain region is equal to or more than about 10 15  units/cm 3 . 
 
     
     
       10. The thin film transistor array panel of claim  1  19, wherein
 the carrier concentration of the channel region is less than about 10 18  units/cm 3 , and the carrier concentration of the source region and the drain region is equal to or more than about 10 18  units/cm 3 . 
 
     
     
       11. The thin film transistor array panel of  claim 1 , wherein
 the gate insulating layer and the gate electrode are disposed on the channel region, and   an edge boundary of the gate electrode, an edge boundary of the gate insulating layer, and an edge boundary of the channel region are substantially aligned with each other.   
     
     
       12. The thin film transistor array panel of  claim 1 , wherein
 the light blocking film includes a metal material.   
     
     
       13. The thin film transistor array panel of  claim 1 , wherein
 an edge boundary of the channel region, an edge boundary of the source region, and an edge boundary of the drain region are located inside an edge boundary of the light blocking film.   
     
     
       14. The thin film transistor array panel of  claim 1 , wherein
 the buffer layer further comprises at least one selected from silicon oxide(SiOx), aluminum oxide(Al 2 O 3 ), hafnium oxide(HfO 3 ), and yttrium oxide(Y 2 O 3 ). 
 
     
     
       15. The thin film transistor array panel of claim  1  21, wherein
 the buffer layer has a thickness of about 500 Å to 10000 Å. 
 
     
     
       16. The thin film transistor array panel of  claim 1 , wherein
 the gate insulating layer includes silicon oxide. 
 
     
     
       17. The thin film transistor array panel of claim  1  16, wherein
 the gate insulating layer has a thickness of about 1000 Å to 5000 Å. 
 
     
     
       18. The thin film transistor array panel of  claim 1 , wherein
 the gate electrode comprises at least two materials selected from a group consisting of aluminum-based metal such as aluminum (Al) or aluminum alloys, a silver-based metal such as silver (Ag) or silver alloys, a copper-based metal such as copper (Cu) or copper alloys, a molybdenum-based metal such as molybdenum (Mo) or molybdenum alloys, chromium (Cr), tantalum (Ta), and titanium (Ti).   
     
     
       19. The thin film transistor array panel of  claim 1 , wherein
 the gate electrode has a multilayered structure including at least two conductive layers having different physical properties from each other.   
     
     
       20. The thin film transistor array panel of claim 1,
 wherein the oxide semiconductor is covered by the light blocking film.   
     
     
       21. The thin film transistor array panel of claim 20, wherein
 the buffer layer further comprises at least one selected from silicon oxide (SiOx), aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 3 ), and yttrium oxide (Y 2 O 3 ).   
     
     
       22. The thin film transistor array panel of claim 15, wherein the buffer comprises silicon oxide (SiOx). 
     
     
       23. The thin film transistor array panel of claim 22, wherein the gate insulating layer includes silicon oxide. 
     
     
       24. The thin film transistor array panel of claim 23, wherein the gate insulating layer has a thickness of about 1000 Å to 5000 Å.