Semiconductor memory device and driving method thereof

Abstract

A semiconductor memory device includes: a variable delay for delaying a delay locked loop (DLL) clock by a predetermined delay time to output a delayed DLL clock; an output driver for outputting data and data strobe signal in response to the delayed DLL clock; and a calibration controller for controlling the predetermined delay time of the variable delay in response to output AC parameters.

What is claimed is: 
     
       1. A semiconductor memory device, comprising:
 a variable delay configured to delay a clock;   an output driver configured to transfer data to a chipset in response to a calibration command received from the chipset and the delayed clock;   an output buffer configured to transfer a data strobe signal to the chipset in response to the calibration command and the delayed clock; and   a calibration controller configured to control the delay time of the variable delay according to output AC parameters measured by the chipset.   
     
     
       2. The semiconductor memory device of  claim 1 , wherein the output driver comprises:
 a pre-driver configured to pre-drive an output data signal; and   a main driver configured to drive a data output terminal in response to an output signal of the pre-driver.   
     
     
       3. The semiconductor memory device of  claim 1 , wherein the output AC parameters include at least one of a parameter representing skew between the data strobe signal and the data, a parameter representing skew between the data strobe signal and a clock, and a parameter representing skew between the data and the clock. 
     
     
       4. A semiconductor memory device, comprising:
 a variable delay configured to delay a clock;   an output driver configured to receive and output data in response to the delayed clock; and   a calibration controller configured to measure AC parameters of data and data strobe signal received from a chipset in response to a calibration command received from the chipset, and control the delay time of the variable delay according to measured values of the output AC parameters.   
     
     
       5. The semiconductor memory device of  claim 4 , wherein the calibration controller comprises:
 a feedback input buffer configured to feed back the data and the data strobe signal, which are transferred to the chipset, in response to a calibration test mode signal generated when the calibration command is received; and   a timing measurer configured to receive the data and the data strobe signal from the feedback input buffer, measure the AC parameters of data and data strobe signal, and control the delay time of the variable delay according to measured values of the output AC parameters.   
     
     
       6. The semiconductor memory device of  claim 4 , wherein the calibration controller comprises:
 a real-time monitor configured to monitor the data and the data strobe signal being transferred to the chipset; and   a timing measurer configured to receive the data and the data strobe signal from the real-time monitor, measure the AC parameters of data and data strobe signal, and control the delay time of the variable delay according to measured values of the output AC parameters.   
     
     
       7. The semiconductor memory device of  claim 4 , wherein the output driver comprises:
 a pre-driver configured to pre-drive an output data signal; and   a main driver configured to drive a data output terminal in response to an output signal of the pre-driver.   
     
     
       8. The semiconductor memory device of  claim 4 , wherein the output AC parameters include at least one of a parameter representing skew between the data strobe signal and the data, a parameter representing skew between the data strobe signal and the clock, and a parameter representing skew between the data and the clock. 
     
     
       9. A method for driving a semiconductor memory device, comprising:
 receiving a calibration command from a chipset;   transferring a first data and a first data strobe signal to the chipset in response to the calibration command;   receiving measured values of output AC parameters from the chipset, wherein the measured values of output AC parameters are measured at the chipset by using the data and the data strobe signal;   setting a delay value with respect to a clock in response to the measured values of the output AC parameters;   delaying the clock by the delay value to output a delayed clock; and transferring a second data and a second data strobe signal having calibrated output AC parameters to the chipset in response to the delayed clock.   
     
     
       10. The method of  claim 9 , further comprising:
 after transferring the second data and the second data strobe signal, remeasuring the output AC parameters at the chipset based on the second data and the second data strobe signal having the calibrated output AC parameters; and   when the remeasured output AC parameters comply with a specification, completing a calibration operation.   
     
     
       11. A method for driving a semiconductor memory device, comprising:
 receiving a calibration command from a chipset;   receiving a first data and a first data strobe signal from the chipset;   measuring AC parameters of the first data and the first data strobe signal in response to the calibration command;   controlling the delay time of a clock according to measured values of the AC parameters; and   transferring a second data and a second data strobe signal having calibrated output AC parameters to the chipset in response to the delayed clock.   
     
     
       12. A memory system including a dynamic access memory and control system, the control system comprising:
 a variable delay unit for delaying a clock signal by a predetermined delay time to output a delayed clock signal;   an output driver for transferring data and a data strobe signal in response to the delayed clock signal; and   a calibration controller for controlling the predetermined delay time of the variable delay according to at least one output AC parameter, wherein the calibration controller comprises:   a real-time monitoring buffer for monitoring the data and the data strobe signal; and   a timing measurer for receiving the data and the data strobe signal from the real-time monitoring buffer and calibrating the predetermined delay time by measuring the at least one output AC parameter and controlling said measured AC parameter.   
     
     
       13. The memory system of claim 12, wherein the calibration controller controls the predetermined delay time according to measured values of the output AC parameters. 
     
     
       14. The memory system of claim 12, wherein the output driver comprises: a pre-driver for pre-driving an output data signal; and a main driver for driving a data output terminal in response to an output signal of the pre-driver. 
     
     
       15. The memory system of claim 12, wherein the calibration controller is configured to receive the at least one output AC parameter, the at least one output AC parameter comprising at least one of a parameter representing skew between a data strobe signal and the data, a parameter representing skew between the data strobe signal and a clock, and a parameter representing skew between the data and the clock. 
     
     
       16. A method for driving a memory system, the system including a dynamic access memory and at least one signal driver outputting data strobe signals and data signals, the method comprising:
 receiving a calibration command from a chipset;   receiving a first data strobe signal and a first data signal from the chipset;   measuring at least one output AC parameter from one of the data strobe signal and data signal;   setting a delay value with respect to a DLL clock signal in response to the measured values of the at least one output AC parameter;   delaying the DLL clock signal by the delay value to output a delayed clock signal to the chipset; and   transferring a second data strobe signal and a second data signal having a calibrated at least one output AC parameter to the chipset in response to the delayed clock signal,   wherein the measuring of the at least one output AC parameter comprises:
 generating a calibration test mode signal in response to a calibration command; 
 feeding back the data and the data strobe signal in response to the calibration test mode signal; and 
 measuring the at least one output AC parameter by using the fed-back data strobe signal and the fed-back data. 
   
     
     
       17. The method of claim 16, wherein the measuring the at least one output AC parameter includes:
 transmitting the data and the data strobe signal in response to the calibration command; and   receiving the at least one output AC parameter measured by using the data strobe signal and the data.   
     
     
       18. The method of claim 16, further comprising completing a calibration operation when the at least one output AC parameter based on the data and the data strobe signal having the calibrated at least one output AC parameter complies with a specification. 
     
     
       19. The method of claim 17, further comprising returning to the step of receiving of the at least one output AC parameter when the at least one output AC parameter, based on the data and the data strobe signal having the calibrated at least one output AC parameter, does not comply with a specification. 
     
     
       20. The method of claim 17, wherein when receiving the at least one output AC parameter, the at least one output AC parameter comprises at least one of a parameter representing skew between the data strobe signal and the data, a parameter representing skew between the data strobe signal and a clock, and a parameter representing skew between the data and the clock.