Semiconductor integrated circuit

Abstract

A semiconductor integrated circuit able to reduce a load of layout design when arranging switches in a power lines for preventing leakage current and able to reduce the influence of a voltage drop occurring in the switches on a signal delay, wherein a plurality of groups of power lines are arranged in stripe shapes, power is supplied to circuit cells by a plurality of groups of branch lines branching from the groups of power lines, power switch cells arranged in the groups of branch lines turn on or off the supply of power to the circuit cells, the power switch cells are arranged dispersed in the area of arrangement of the circuit cells, and the supply of power by the power switch cells is finely controlled for every relatively small number of circuit cells.

The invention claimed is: 
     
       1. A semiconductor integrated circuit comprising:
 a first branch line adapted to provide a potential to a first circuit cell, a power line being at said potential;   a second branch line adapted to provide said potential to a second circuit cell; and   a third branch line adapted to provide another potential to said first and second circuit cells, another power line being at said another potential,   wherein an electrical connection between said first branch line and said power line is controlled in accordance with a state of a control signal.   
     
     
       2. A semiconductor integrated circuit as set forth in  claim 1 , wherein said first circuit cell and said second circuit cell can be arranged mixed at any positions on said first and second branch lines. 
     
     
       3. A semiconductor integrated circuit as set forth in  claim 1 , wherein said potential is VSS. 
     
     
       4. A semiconductor integrated circuit as set forth in  claim 1 , wherein an interconnection between said power line and said second branch line is present regardless of said state of the control signal. 
     
     
       5. A semiconductor integrated circuit as set forth in  claim 1 , wherein said another potential is VDD. 
     
     
       6. A semiconductor integrated circuit as set forth in  claim 1 , wherein said third branch line connects said another power line to said first and second circuit cells regardless of said state of the control signal. 
     
     
       7. A semiconductor integrated circuit as set forth in  claim 1 , further comprising:
 a power switch cell adapted to control said electrical connection between said first branch line and said power line.   
     
     
       8. A semiconductor integrated circuit as set forth in  claim 7 , wherein said power switch cell comprises:
 a first interconnect line connected to said first branch line;   a second interconnect line connected to said power line; and   a switch circuit between said first interconnect line and said second interconnect line connecting said first interconnect line to said second interconnect line in accordance with said state of the control signal.   
     
     
       9. A semiconductor integrated circuit comprising:
 power lines extending along a power line direction, the power line direction is other than a branch line direction;   branch lines extending along the branch line direction, a first one of the branch lines and a second one of the branch lines are electrically connected to a first one of the power lines;   a first circuit cell between a third one of the branch lines and the first one of the branch lines, the third one of the branch lines is between the first one of the branch lines and the second one of the branch lines;   a power switch cell that is controllable to provide electrical connection and disconnection between a second one of the power lines and the third one of the branch lines, the third one of the branch lines and the first one of the branch lines are electrically connected directly to the first circuit cell; and   a second circuit cell between the third one of the branch lines and the second one of the branch lines, the second circuit cell is electrically connected directly to the third one of the branch lines and the second one of the branch lines.    
     
     
       10. A semiconductor integrated circuit as set forth in claim 9, wherein the power line direction is perpendicular to the branch line direction.  
     
     
       11. A semiconductor integrated circuit as set forth in claim 9, wherein the power switch cell is in an area under the second one of the power lines.  
     
     
       12. A semiconductor integrated circuit as set forth in claim 9, further comprising:
 a first interconnect line that electrically connects a first one of the branch lines to a first one of the power lines.    
     
     
       13. A semiconductor integrated circuit as set forth in claim 12, further comprising:
 a second interconnect line that electrically connects a second one of the branch lines to the first one of the power lines.