Generation of digital clock for system having RF circuitry

Abstract

Circuitry for any of a transceiver, a transmitter, and a receiver, has radio frequency (RF) circuitry, digital circuitry, a carrier signal generator to provide a carrier signal to the RF circuitry and a clock generator for generating a digital clock for clocking at least some of the digital circuitry. The RF circuitry is susceptible to interference from harmonics of the clocking, and the clock generator derives a frequency of the digital clock based on a frequency divided down from a frequency of the carrier signal so that the interference to the RF circuitry occurs at frequencies which are harmonics of the carrier signal.

What is claimed is: 
     
       1. Circuitry for any of a transceiver, a transmitter, and a receiver, the circuitry comprising:
 radio frequency (RF) circuitry; 
 digital circuitry; 
 a carrier signal generator; 
 a clock generator to generate a digital clock for clocking the digital circuitry; and 
 a fallback oscillator, 
 wherein the RF circuitry is susceptible to interference from harmonics of the clocking of the digital circuitry, 
 wherein the carrier signal generator is coupled to provide a carrier signal to the RF circuitry, 
 wherein the clock generator is arranged to derive a frequency of the digital clock based on a frequency divided down from a frequency of the carrier signal such that the interference to the RF circuitry occurs at frequencies that are harmonics of the carrier signal, wherein the fallback oscillator generates a fallback reference frequency, 
 wherein the clock generator has a fallback selector to select the fallback reference frequency as a source from which to generate the digital clock when the carrier frequency is not suitable, wherein the fallback selector has a monitor to monitor a stability of the carrier signal, and 
 wherein the fallback selector is operable to select the fallback reference frequency depending on the stability of the carrier signal. 
 
     
     
       2. The circuitry of  claim 1 , wherein the clock generator has one or more programmable frequency dividers to generate the digital clock. 
     
     
       3. The circuitry of  claim 1 , wherein the clock generator comprises:
 two or more oscillators to generate the carrier signal at different carrier frequencies; and 
 a selector to select which of the carrier frequencies is used as a source to generate the digital clock. 
 
     
     
       4. The circuitry of  claim 1 , wherein the digital circuitry clocked by the digital clock comprises any one or more of: analog to digital conversion circuitry for received signals, digital to analog conversion circuitry for transmitted signals, digital processing circuitry for processing the received or transmitted signals, and a digital part of the clock generator. 
     
     
       5. The circuitry of  claim 1 , further comprising a digital compensation circuit to digitally compensate at least some of the digital processing circuitry clocked by the digital clock based on a change in the frequency of the digital clock. 
     
     
       6. The circuitry of  claim 5 , wherein the digital compensation circuit comprises a digital resampling circuit to carry out resampling by a ratio inversely proportional to the change in frequency of the digital clock. 
     
     
       7. Circuitry for any of a transceiver, a transmitter, and a receiver, the circuitry comprising:
 radio frequency (RF) circuitry; 
 digital circuitry; 
 a carrier signal generator; and 
 a clock generator to generate a digital clock for clocking the digital circuitry, 
 wherein the RF circuitry is susceptible to interference from harmonics of the clocking of the digital circuitry, 
 wherein the carrier signal generator is coupled to provide a carrier signal to the RF circuitry, 
 wherein the clock generator is arranged to derive a frequency of the digital clock based on a frequency divided down from a frequency of the carrier signal such that the interference to the RF circuitry occurs at frequencies that are harmonics of the carrier signal, 
 wherein the clock generator has a controller to select a change in frequency of the digital clock based on a quality of an output of digital processing of received or transmitted signals clocked by the digital clock and based on the interference caused by the clocking, and 
 wherein the controller is configured to:
 estimate a digital clock rate needed by a respective type of digital receiver processing to achieve a predetermined minimum signal to noise ratio for a signal being received; and 
 determine whether the interference caused by that estimated digital clock rate is within an acceptable threshold as a basis for selecting a change in frequency for the digital clock. 
 
 
     
     
       8. A method of generating a digital clock for clocking digital circuitry associated with any of a transceiver, a transmitter, and a receiver, the method comprising:
 generating a carrier signal for radio frequency (RF) circuity, wherein the RF circuitry is susceptible to interference from harmonics of the clocking of the digital circuitry; 
 deriving a frequency of the digital clock based on a frequency divided down from a frequency of the carrier signal such that the interference to the RF circuitry occurs at frequencies which are harmonics of the carrier signal; 
 programming one or more programmable frequency dividers to alter the frequency of the digital clock; 
 estimating a digital clock frequency needed by a respective type of digital receiver processing to achieve a predetermined minimum signal to noise ratio for a signal being received; 
 determining whether the interference caused by that estimated digital clock frequency is within an acceptable threshold; and 
 selecting a change in frequency for the digital clock based on whether the interference caused by the estimated clock frequency is within the acceptable threshold. 
 
     
     
       9. The method of  claim 8 , further comprising:
 generating two or more carrier signals at different carrier frequencies; and 
 selecting which of the carrier frequencies is used as a source to generate the digital clock. 
 
     
     
       10. The method of  claim 8 , further comprising resampling a digital signal used by the digital circuitry by a ratio inversely proportional to the change in frequency of the digital clock. 
     
     
       11. The method of  claim 8 , further comprising compensating for the interference in the RF circuitry from the harmonics of the clocking of the digital circuitry. 
     
     
       12. Circuitry comprising:
 two or more oscillators;   a clock generator coupled to the oscillators;   first digital circuitry coupled to the clock generator; and   second digital circuitry coupled to the clock generator;   wherein the clock generator comprises a selector, a first frequency divider, and a second frequency divider,   wherein the first frequency divider and the second frequency divider are coupled to the oscillators,   wherein the first frequency divider is configured to provide a first clock signal to the first digital circuitry,   wherein the second frequency divider is configured to provide a second clock signal to the second digital circuitry,   wherein the selector is configured to select which of the two or more oscillators is used as a source to generate the first clock signal and the second clock signal, and comprises a monitor to monitor stability of signals from the oscillators.   
     
     
       13. The circuitry of claim 12, further comprising radio frequency (RF) circuitry, wherein one of the oscillators is configured to provide a carrier signal to the RF circuitry. 
     
     
       14. The circuitry of claim 12, wherein the first digital circuitry further comprises an analog-to-digital converter (ADC), and wherein the second digital circuitry comprises a digital-to-analog converter (DAC).