Electronic-integration compatible photonic integrated circuit and method for fabricating electronic-integration compatible photonic integrated circuit

Abstract

An electronic-integration compatible photonic integrated circuit (EIC-PIC) for achieving high-performance computing and signal processing is provided. The electronic-integration compatible photonic integrated circuit comprises a plurality of electronic circuit structures and a plurality of photonic circuit structures. The electronic and photonic circuit structures are integrated by a process referred to as monolithic integration. An electronic circuit structure includes one or more electronic devices and a photonic circuit structure includes one or more photonic devices. The integration steps of electronic and photonic devices are further inserted into standard CMOS process. The photonic circuit structures and the electronic circuit structures are integrated to form the electronic-integration compatible photonic integrated circuit device.

What is claimed is: 
     
       1. A method for integrating one or more photonic devices on a substrate with a semiconductor device, wherein the semiconductor device comprises one or more electronic devices, the method comprising:
 a. creating a first optical cladding layer on a first substrate;   b. creating a first optical core layer on top of the first optical cladding layer, wherein the first optical cladding layer and the first optical core layer form a first optical waveguide;   c. creating a first optical-fiber coupling lens on the first optical waveguide;   d. creating a first optical device, wherein an optical beam in the first waveguide propagates substantially in the first optical core layer;   e. optically connecting the first optical device to the first waveguide;   f. creating a first interspaced dielectric structure layer on top of the first optical core layer;   g. creating a second optical core layer on top of the first interspaced dielectric structure layer; and   h. creating a second optical device with optical beam propagating substantially in the second optical core layer;   i. mounting a first optical fiber on the first substrate to facilitate a coupling of light beam energy between the first optical fiber and the first optical waveguide.   
     
     
       2. The method of  claim 1 , wherein the first substrate is a silicon-on-insulator wafer, the first optical cladding layer is a silicon dioxide layer, and the first optical core layer is a silicon-on-insulator wafer. 
     
     
       3. The method of  claim 1 , wherein the first optical-fiber coupling lens is a superlens. 
     
     
       4. The method of  claim 1 , wherein the first optical device is one of an optical waveguide, an optical wavelength multiplexer, an optical wavelength demultiplxer, an optical grating, an optical beam splitter, a polarization beam splitter, an optical isolator, a polarization rotator, an optical interferometer, an optical modulator, an optical ring resonator, an optical disk resonator, an optical curved reflector, an optical mirror, an optical amplifier, an optical detector, a laser, a light-emitting device, a nonlinear-optical device, a photonic transistor, a optical harmonic frequency generator, and an all-optical device. 
     
     
       5. The method of  claim 1 , wherein the first substrate comprises a trench to support the optical fiber. 
     
     
       6. The method of  claim 1 , wherein the first substrate comprises a V-groove to support the optical fiber. 
     
     
       7. The method of  claim 1 , wherein the optical beam enters the second optical device through a tapered waveguide structure made from the second optical core layer. 
     
     
       8. The method of  claim 1 , wherein the optical beam exits the second optical device through a tapered waveguide structure made from the second optical core layer. 
     
     
       9. The method of  claim 1 , wherein the second optical core layer is fabricated by wafer bonding. 
     
     
       10. The method of  claim 1 , wherein the second optical core layer is fabricated by local-area wafer bonding. 
     
     
       11. The method of  claim 10 , wherein the steps a-e are performed by using a process used in fabricating electronic devices. 
     
     
       12. The method of  claim 1 , wherein the electronic devices are one of an electronic transistor, an electronic diode, a resistor, a capacitor, or an inductor. 
     
     
       13. The method of  claim 1 , wherein the electronic devices form a CMOS integrated circuit. 
     
     
       14. The method of  claim 1 , wherein the semiconductor device comprises one or more Complementary Metal-Oxide-Semiconductor (CMOS) devices, the method further comprising:
 a. growing a first dielectric layer and a second dielectric layer on a nano-waveguide and a disk;   b. creating a deposition layer on the first dielectric layer and the second dielectric layer;   c. creating a source region and a drain region by implanting N+ dopants and P+ dopants on the deposition layer, wherein an integrated structure is formed.   
     
     
       15. The method of  claim 14 , wherein the one or more Complementary Metal-Oxide-Semiconductor (CMOS) devices are integrated by using a standard CMOS fabrication process. 
     
     
       16. The method of  claim 1 , wherein the second optical core layer is a III-V compound semiconductor layer. 
     
     
       17. The method of  claim 1  further comprising performing Quantum Well Intermixing (QWI) on the second optical core layer. 
     
     
       18. A semiconductor device manufactured by the method as claimed in  claim 14 . 
     
     
       19. The semiconductor device of  claim 18  further comprising a plurality of electronic circuit structures. 
     
     
       20. The semiconductor device of  claim 19 , wherein the plurality of electronic circuit structures further comprise at least one of an active electronic device and a passive electronic device. 
     
     
       21. The semiconductor device of  claim 18  further comprising a plurality of photonic circuit structures. 
     
     
       22. The semiconductor device of  claim 21 , wherein the plurality of photonic circuit structures further comprise at least one of an active photonic device and a passive photonic device. 
     
     
       23. A method for integrating one or more photonic devices on a substrate, the method comprising:
 a. providing a substrate with one or more electronic devices on one or more connected or disjointed electronic device areas on a first substrate;   b. providing an area of the first substrate having a layer structure with a first optical cladding layer and a first optical core layer, wherein part of the first optical cladding layer and the first optical core layer form a first optical waveguide;   c. providing a first optical device;   d. optically connecting the first optical device to the first waveguide;   e. creating a second optical core layer above the first waveguide via a local-area wafer bonding process comprising:
 i. creating a first material layer structure on a second substrate, wherein the first material layer structure comprises plurality of material layers in which at least one of the plurality of material layers comprises a second optical core layer, 
 ii. attaching a handling fixture to the first material layer structure, 
 iii. removing the second substrate, leaving the handling fixture attached to the first material layer structure without the second substrate such that one or more areas on the first material layer structure, that will not be used for fabricating photonic devices and will later cover over the first electronic device areas during the wafer bonding process, are pre-etched away with indentation; and 
   f. bonding the first material structure to the top surface of the first waveguide either directly or via an additional dielectric layer between the first material layer structure and the first optical core.   
     
     
       24. The method of claim 23, further comprising creating the first optical device along with the first optical core layer such that an optical beam in the first optical device propagates substantially in the first optical core layer. 
     
     
       25. The method of claim 24, wherein the first optical device is one of an optical waveguide, an optical wavelength multiplexer, an optical wavelength demultiplexer, an optical grating, an optical beam splitter, a polarization beam splitter, an optical isolator, a polarization rotator, an optical interferometer, an optical modulator, an optical ring resonator, an optical disk resonator, an optical curved reflector, an optical mirror, an optical amplifier, an optical detector, a laser, a light-emitting device, a nonlinear-optical device, a photonic transistor, an optical harmonic frequency generator, and an all-optical device. 
     
     
       26. The method of claim 23, further comprising creating a second optical device along with the second optical core layer such that an optical beam in the second optical device propagates substantially in the second optical core layer. 
     
     
       27. The method of claim 23 wherein the first optical cladding layer is air or dielectric material. 
     
     
       28. The method of claim 23, wherein one or more electronic devices or one or more photonic devices are created on the substrate or any of the optical layers. 
     
     
       29. The method of claim 28, wherein the electronic devices are one of an electronic transistor, an electronic diode, a resistor, a capacitor, or an inductor. 
     
     
       30. The method of claim 28, wherein the electronic devices form a CMOS integrated circuit. 
     
     
       31. The method of claim 28, wherein the semiconductor device comprises one or more Complementary Metal-Oxide-Semiconductor (CMOS) devices, the method further comprising:
 a. growing a first dielectric layer and a second dielectric layer on a nano-waveguide and a disk;   b. creating a deposition layer on the first dielectric layer and the second dielectric layer; and   c. creating a source region and a drain region by implanting N+ dopants and P+ dopants on the deposition layer, wherein an integrated structure is formed.   
     
     
       32. The method of claim 31, wherein the one or more Complementary Metal-Oxide-Semiconductor (CMOS) devices are integrated by using a standard CMOS fabrication process. 
     
     
       33. A semiconductor device manufactured by the method as claimed in claim 31. 
     
     
       34. The semiconductor device of claim 33 further comprising a plurality of electronic circuit structures. 
     
     
       35. The semiconductor device of claim 34, wherein the plurality of electronic circuit structures further comprise at least one of an active electronic device and a passive electronic device. 
     
     
       36. The semiconductor device of claim 33 further comprising a plurality of photonic circuit structures. 
     
     
       37. The semiconductor device of claim 36, wherein the plurality of photonic circuit structures further comprise at least one of an active photonic device and a passive photonic device. 
     
     
       38. The method of claim 23, wherein the first substrate is a silicon-on-insulator wafer, the first optical cladding layer is a silicon dioxide layer, and the first optical core layer is the top silicon layer of a silicon-on-insulator wafer. 
     
     
       39. The method of claim 23, wherein the first substrate comprises a trench to support an optical fiber. 
     
     
       40. The method of claim 23, wherein the first substrate comprises a V-groove to support an optical fiber. 
     
     
       41. The method of claim 23, wherein the optical beam enters the second optical device through a tapered waveguide structure made from the second optical core layer. 
     
     
       42. The method of claim 23, wherein the optical beam exits the second optical device through a tapered waveguide structure made from the second optical core layer. 
     
     
       43. The method of claim 23, wherein the steps a-d are performed by using a process used in fabricating electronic devices. 
     
     
       44. The method of claim 23, wherein the second optical core layer is a III-V compound semiconductor layer. 
     
     
       45. The method of claim 23 further comprising performing Quantum Well Intermixing (QWI) on the second optical core layer. 
     
     
       46. The method of claim 23, wherein a first coupling lens further couples light between an optical fiber and a waveguide on the substrate. 
     
     
       47. The method of claim 46, wherein the first optical-fiber coupling lens is a superlens. 
     
     
       48. The method of claim 46, wherein the first coupling lens is a superlens and the superlens has a width WSPL, height HSPL and length LSPL fabricated on top of the waveguide by depositing multi-layers of alternating dual materials. 
     
     
       49. The method of claim 48, wherein the dual materials are Silicon (Si) and Silicon Dioxide (SiO2). 
     
     
       50. The method of claim 48, wherein the superlens dimensions are WSPL=20 μm, HSPL=15 μm, and LSPL=20 μm. 
     
     
       51. The method of claim 49, wherein the thickness ratio of Silicon to Silicon Dioxide is varied such that the effective index of the superlens is n=3.5 at the bottom of the lens near the surface of the waveguide and is at least partially of silicon, and the effective index of the superlens is n=1.5 near the top of the superlens and is at least partially of silicon dioxide. 
     
     
       52. The method of claim 46, wherein the optical fiber is an optical fiber with a full-width-half maximum (FWHM) mode size diameter of 8 μm. 
     
     
       53. The method of claim 51, wherein the index variation of the superlens is such that the mode from the waveguide will expand in the lens such that the strong lensing effect in the superlens results in an output beam of a larger diameter. 
     
     
       54. The method of claim 53, wherein the wavefront is a flat wavefront at the output surface of the superlens. 
     
     
       55. The method of claim 46, wherein the optical fiber is held from below by a structure having a V-groove or a trench configuration, fabricated on the substrate that holds the optical fiber at the right height with respect to the lens optical center to achieve maximum coupling of light beam energy between the optical fiber and the waveguide on chip. 
     
     
       56. The method of claim 55, wherein the structure is a trench of rectangular shape or of a shape adapted to hold the fiber in steady position. 
     
     
       57. The method of claim 55 wherein additional materials between substrate and fiber hold the fiber in place. 
     
     
       58. The method of claim 23, wherein the Bonding process is one that involves at least the following steps:
 a. making a material layer structure on top of a wafer substrate, the material layer including an etch-stop layer first made on the substrate;   b. making a structure containing the second optical core layer on top of the etch-stop layer;   c. bonding a handling wafer to the second optical core layer side of the wafer, exposing the substrate;   d. etching the exposed substrate by an etching process that stops at the etch-stop layer, resulting in a new exposed surface;   e. initiating a wafer bonding process by pressing the new exposed surface onto the material at the top surface of the first optical core layer under pressure and elevated temperature;   f. removing the handling wafer resulted in the second optical core layer above the first optical core layer.   
     
     
       59. The method of claim 58, wherein the wafer substrate is indium phosphide (InP). 
     
     
       60. The method of claim 59, wherein the etch-stop layer in claim 59 is InGaAsP compound semiconductor material. 
     
     
       61. The method of claim 58, wherein the second optical core layer is an active optical material layer. 
     
     
       62. The method of claim 61, wherein the second optical core layer contains semiconductor quantum wells. 
     
     
       63. The method of claim 58, wherein the etched stop layer and active optical material layer are grown epitaxially on top of an InP substrate. 
     
     
       64. The method of claim 58, wherein the handling wafer is bonded to the second optical core layer side of the wafer using Benzocyclobutene (BCB) polymer. 
     
     
       65. The method of claim 58, wherein the etching process of step (d) of claim 58 is a selective chemical etching process that etches an InP substrate material at a rate faster than etching an etch-stop InGaAsP layer material. 
     
     
       66. The method of claim 65, wherein the chemical etching is done by hydrochloric acid (HCl). 
     
     
       67. The method of claim 58, wherein after the wafer bonding, resulted in a Direct Double Optical Layer structure for an Electronic Integration Compatible Photonic Integrated Circuit (DDOL-EIC-PIC). 
     
     
       68. The method of claim 58, wherein a thin interspaced dielectric layer is grown on the new exposed surface of step (d) and a thin interspaced dielectric layer is also grown on the top surface of the first optical core. 
     
     
       69. The method of claim 68, the interspaced dielectric layer is silicon nitride. 
     
     
       70. The method of claim 58, wherein in step (e), wafer bonding process is initiated by pressing the thin interspaced dielectric layer on the new exposed surface of step (d) against the interspaced dielectric layer on the top surface of the first optical core under external pressure and elevated temperature. 
     
     
       71. The method of claim 70, wherein the wafer bonding, results in an Indirect Double Optical Layer structure for an Electronic Integration Compatible Photonic Integrated Circuit (IDDOL-EIC-PIC). 
     
     
       72. The method of claim 58, wherein in step (e) of claim 58, the surfaces to be bonded is subjected to the plasma treatment to create hydrophilic surfaces before bonding. 
     
     
       73. The method of claim 72, wherein the plasma treatment is achieved with 1-minute exposure to oxygen plasma. 
     
     
       74. The method of claim 70, wherein the interspaced dielectric layer surfaces to be bonded is subjected to the plasma treatment to create hydrophilic surfaces before bonding. 
     
     
       75. The method of claim 74, wherein the plasma treatment is achieved with 1-minute exposure to oxygen plasma. 
     
     
       76. The method of claim 58, wherein in step (e), the bonding is achieved at an elevated temperature above 150° C. and less than 400° C. 
     
     
       77. The method of claim 58, wherein the handling wafer is InP wafer and is selectively etched away using HCL in step (f). 
     
     
       78. The method of claim 23, wherein the wafer bonding involves a second wafer made with the second optical core layer with a second surface. 
     
     
       79. The method of claim 78, wherein the top exposed surface of the first optical core layer on the substrate is the first surface, and wafer bonding involves pressing the second surface of the second optical core layer onto the first surface of the first optical core layer under pressure and elevated temperature. 
     
     
       80. The method of claim 79, wherein before the pressing of the two surfaces, certain areas of the second surface that are not later be fabricated with photonic devices are pre-etched away with indentations resulting in a new second surface in such a way that the during the pressing down process, the new second surface touches only the area designated as photonic areas on the substrate wafer and not the electronic areas on the substrate wafer. 
     
     
       81. The method of claim 80, wherein the wafer bonding process resulted in local-area wafer bonding in which one or plurality of areas designed as the photonic areas are bonded with the second optical core layer. 
     
     
       82. The method of claim 23 wherein an additional step is added that includes covering the photonic areas with protective materials during the high-temperature electronic fabrication or CMOS process, and then uncover the protected photonic areas by removing the photonic-area protective materials so that a fresh silicon surface is uncovered for performing the wafer bonding. 
     
     
       83. The method of claim 82 wherein the protective material is In2O3. 
     
     
       84. The method of claim 62 wherein a quantum-well intermixing process to shift the bandgap energy of the quantum well is performed before the wafer bonding. 
     
     
       85. The method of claim 84 wherein the quantum well intermixing is “low-energy temperature-assisted ion-implantation quantum well intermixing” (LETAI-QWI). 
     
     
       86. The method of claim 62 wherein a quantum-well intermixing process to shift the bandgap energy of the quantum well is performed after the wafer bonding. 
     
     
       87. The method of claim 86 wherein the quantum well intermixing is “low-energy temperature-assisted ion-implantation quantum well intermixing” (LETAI-QWI). 
     
     
       88. The method of claim 23, wherein the second optical core layer is made of material selected from the group consisting of: Indium Phosphide (InP), Gallium Arsenide (GaAs), Indium Gallium Arsenide (InGaAs), Indium Gallium Arsenide Phosphide (InGaAsP), Indium Aluminum Gallium Arsenide (InAlGaAs), Aluminum Arsenide (AlAs), Aluminum Gallium Arsenide (AlGaAs), Indium Gallium Aluminum Phosphide (InGaAlP), Indium Gallium Phosphide (InGaP), Gallium Nitride (GaN), Aluminum Nitride (AIN), Gallium Aluminum Nitride (GaAlN), Gallium Phosphide (GaP), Aluminum Phosphide (AlP), Aluminum Antimonide (AlSb), Gallium Antimonide (GaSb), Zinc selenide (ZnSe), Zinc Sulphide (ZnS), Cadmium Sulphide (CdS), Silicon Carbide (SiC), Silicon Germanium (SiGe), Indium Gallium Antimonide (InGaSb), or Indium Antimonide (InSb), Germanium (Ge), Silicon-Germanium (SiGe), or two or more of the combinations thereof. 
     
     
       89. The method of claim 23, wherein the dielectric material layer including the first optical cladding layer and the first optical core layer are made of material selected from the group consisting of: tantalum pentoxide (Ta2O5), zirconium oxide (ZrO2), niobium pentoxide (Nb2O5), hafnium oxide (HfO2), zinc oxide (ZnO), germanium oxide (GeO2), lead oxide (PbO), yttrium oxide (Y2O3), aluminum oxide (Al2O3), silicon carbide (SiC), titanium carbide (TiC), titanium nitride (TiN), chromium nitride (CrN), carbon nitride (CN), carbon boride (CB), aluminum nitride (AlN), zinc selenide (ZnSe), barium fluoride (BaF2), magnesium fluoride (MgF2), Diamond like Carbon (DLC), Benzocyclobutene (BCB), cyclized transparent optical polymer (CYTOP), or a polymer of imide monomers (Polyimide), or two or more of the combinations thereof.