Metal assisted chemical etching to produce III-V semiconductor nanostructures

Abstract

Methods of metal assisted chemical etching III-V semiconductors are provided. The methods can include providing an electrically conductive film pattern disposed on a semiconductor substrate comprising a III-V semiconductor. At least a portion of the III-V semiconductor immediately below the conductive film pattern may be selectively removed by immersing the electrically conductive film pattern and the semiconductor substrate into an etchant solution comprising an acid and an oxidizing agent having an oxidation potential less than an oxidation potential of hydrogen peroxide. Such methods can form high aspect ratio semiconductor nanostructures.

The invention claimed is: 
     
       1. A method of metal assisted chemical etching, the method comprising:
 providing an electrically conductive film pattern disposed on a semiconductor substrate, the semiconductor substrate comprising a III-V semiconductor; and 
 selectively removing at least a portion of the III-V semiconductor immediately below the conductive film pattern by immersing the electrically conductive film pattern and the semiconductor substrate into an etchant solution comprising an acid and an oxidizing agent having an oxidation potential less than an oxidation potential of hydrogen peroxide. 
 
     
     
       2. The method of  claim 1 , wherein the etchant solution does not remove substantial portions of the III-V semiconductor which do not have the conductive film pattern disposed thereon. 
     
     
       3. The method of  claim 1 , wherein the III-V semiconductor comprises GaAs. 
     
     
       4. The method of  claim 1 , wherein the III-V semiconductor is doped. 
     
     
       5. The method of  claim 1 , wherein the conductive film comprises gold. 
     
     
       6. The method of  claim 1 , wherein the oxidizing agent comprises potassium permanganate (KMnO 4 ). 
     
     
       7. The method ofclaim  1 , wherein the acid is selected from the group consisting of sulfuric acid (H 2 SO 4 ) and hydrofluoric acid (H F). 
     
     
       8. The method of  claim 1 , further comprising varying a concentration of the oxidizing agent in the etchant solution. 
     
     
       9. The method of  claim 1 , wherein the selectively removing the portion of the III-V semiconductor takes place at a temperature of from about 40° C. to about 45° C. 
     
     
       10. The method of  claim 1 , wherein the conductive film pattern and the semiconductor substrate are immersed in the etchant solution for about 3 to about 5 minutes. 
     
     
       11. The method of  claim 1 , further comprising:
 generating holes (h + ) from the oxidizing agent on the conductive film pattern; 
 diffusing the holes (h + ) to a boundary of the conductive film pattern, III-V semiconductor, and etchant solution; and 
 removing the holes (h + ) from semiconductor substrate substantially immediately upon the holes (h + ) reaching the boundary. 
 
     
     
       12. The method of  claim 1 , further comprising forming features in the semiconductor substrate having a length-to-width aspect ratio of at least about 5:1, thereby forming an array of high aspect ratio semiconductor nanostructures. 
     
     
       13. The method of  claim 12 , wherein the array of high aspect ratio semiconductor nanostructures is an ordered array of nanowires. 
     
     
       14. The method of  claim 1 , wherein a concentration of the oxidizing agent in the etchant solution is in a range of from about 20 mM to about 150 mM. 
     
     
       15. A method of metal assisted chemical etching,
 the method comprising: 
 providing a conductive film pattern disposed on a semiconductor substrate, the semiconductor substrate comprising a III-V semiconductor; and 
 selectively removing at least a portion of the III-V semiconductor immediately below the conductive film pattern by immersing the conductive film pattern and the semiconductor substrate into an etchant solution comprising an acid and an oxidizing agent selected from the group consisting of potassium permanganate (KMnO 4 ) and potassium persulfate (K 2 S 2 O 8 ). 
 
     
     
       16. The method of  claim 15 , wherein the III-V semiconductor comprises gallum arsenide. 
     
     
       17. The method of  claim 15 , wherein a concentration of the oxidizing agent in the etchant solution is in a range of from about 20 mM to about 150 mM. 
     
     
       18. The method of  claim 15 , wherein the selectively removing the portion of the III-V semiconductor takes place at a temperature of from about 40° C. to about 45° C. 
     
     
       19. An electronic device comprising:
 an array of nanopillars protruding from a base substrate, each nanopillar having a quantum well structure comprising a portion of the base substrate, a second layer on the base substrate and a first layer on the second layer,   wherein the first layer comprises a p-type or an n-type III-V semiconductor, the second layer comprises a semi-insulating III-V semiconductor, and the base substrate comprises a p-type or an n-type III-V semiconductor opposite to that of the first layer.    
     
     
       20. The electronic device of claim 19, wherein the III-V semiconductor is selected from the group consisting of GaAs, InAs, GaP, InP, InGaAs and InGaP.  
     
     
       21. The electronic device of claim 19, wherein the nanopillars have a width or diameter in a range from about 10 nm to about 1000 nm.  
     
     
       22. The electronic device of claim 21, wherein the width or diameter is in the range from about 500 nm to about 1000 nm.  
     
     
       23. The electronic device of claim 19, further comprising an electrically insulating material on the base substrate, the electrically insulating material surrounding each nanopillar and extending from the base substrate to a tip portion of the first layer.  
     
     
       24. The electronic device of claim 23, further comprising an electrically conductive material on the tip portion of the first layer.  
     
     
       25. The electronic device of claim 24, wherein the electrically conductive material comprises an electrically conductive transparent oxide, and wherein the electrically insulating material comprises an oxide or a polymer.  
     
     
       26. The electronic device of claim 25, wherein the polymer comprises a photopolymer.  
     
     
       27. The electronic device of claim 19, wherein the nanopillars comprise a length-to-width aspect ratio of at least about 5:1.  
     
     
       28. The electronic device of claim 19, wherein the first layer comprises p-type GaAs, the second layer comprises intrinsic GaAs or intrinsic InGaAs, and the base substrate comprises n-type GaAs.  
     
     
       29. The electronic device of claim 19 being selected from the group consisting of LED, solar cell and laser.