Systems and methods for minimizing static leakage of an integrated circuit

Abstract

A leakage manager system for adequately minimizing static leakage of an integrated circuit is disclosed. The leakage manager system includes a generator configured to generate a control signal to be applied to a sleep transistor. A monitor is configured to determine whether to adjust the control signal to adequately minimize the static leakage. In some embodiments, the monitor includes an emulated sleep transistor. A regulator is configured to adjust the control signal depending on the determination.

What is claimed is: 
     
       1. An integrated circuit comprising:
 a logic component, the logic component being either a logic gate or a storage cell, and the logic component including a sleep transistor in series with an electrical connection to a ground terminal;   a voltage generator configured to generate a negative voltage to be applied to the sleep transistor; and   controller circuitry configured to:   i) monitor drain-source current of the sleep transistor;   ii) make a determination of whether to adjust the negative voltage in connection with adequate minimization of a static leakage of the integrated circuit; and   iii) adjust the negative voltage depending on the determination.   
     
     
       2. The integrated circuit of  claim 1  wherein the controller circuitry is configured to continuously make determinations of whether to adjust the negative voltage in connection with the adequate minimization of the static leakage. 
     
     
       3. The integrated circuit of  claim 1  wherein the controller circuitry is configured to periodically make determinations of whether to adjust the negative voltage in connection with the adequate minimization of the static leakage. 
     
     
       4. The integrated circuit of  claim 1  wherein the voltage generator is configured to selectively generate the negative voltage. 
     
     
       5. The integrated circuit of  claim 1  wherein the voltage generator is a charge pump. 
     
     
       6. An integrated circuit comprising:
 a logic component, the logic component being either a logic gate or a storage cell, and the logic component including;  
 a sleep transistor in series with the logic component and an electrical connection to a ground terminal; 
 a voltage generator configured to generate a negative voltage to be applied to the sleep transistor; and 
 controller circuitry configured to, while the logic component is in a standby mode:
 i) monitor a drain-source current and a drain-gate current of either the sleep transistor or through an emulated sleep transistor; 
 ii) make a determination of whether to adjust the negative voltage in connection with adequate minimization of a static leakage of the integrated circuit; and 
 iii) adjust generate a control signal for adjusting the negative voltage depending on the determination. 
 
 
     
     
       7. The integrated circuit of  claim 6  wherein the controller circuitry is configured to continuously make determinations of whether to adjust the negative voltage in connection with the adequate minimization of the static leakage. 
     
     
       8. The integrated circuit of  claim 6  wherein the controller circuitry is configured to periodically make determinations of whether to adjust the negative voltage in connection with the adequate minimization of the static leakage. 
     
     
       9. The integrated circuit of  claim 6  wherein the voltage generator is configured to selectively generate the negative voltage. 
     
     
       10. The integrated circuit of  claim 6  wherein the voltage generator is a charge pump. 
     
     
       11. An integrated circuit comprising:
 a logic component, the logic component being either a logic gate or a storage cell, and the logic component including;  
 a sleep transistor in series with the logic component and an electrical connection to a ground terminal; 
 a voltage generator configured to generate a negative voltage to be applied to the sleep transistor; and 
 controller circuitry configured to, while the logic component is in a standby mode:
 i) induce produce a current through an emulated sleep transistor in proportion to a static leakage current of the integrated circuit; 
 ii) make a determination of whether to adjust the negative voltage depending on the amount of the current; and 
 iii) adjust generating a control signal for adjusting the negative voltage depending on the determination. 
 
 
     
     
       12. The integrated circuit of  claim 11  wherein the controller circuitry is configured to continuously make determinations of whether to adjust the negative voltage. 
     
     
       13. The integrated circuit of  claim 11  wherein the controller circuitry is configured to periodically make determinations of whether to adjust the negative voltage. 
     
     
       14. The integrated circuit of  claim 11  wherein the voltage generator is configured to selectively generate the negative voltage. 
     
     
       15. The integrated circuit of  claim 11  wherein the voltage generator is a charge pump. 
     
     
       16. An integrated circuit comprising:
 a logic component, the logic component being either a logic gate or a storage cell, and the logic component including;  
 a sleep transistor in series with the logic component and an electrical connection to a ground terminal; 
 a voltage generator configured to generate a negative voltage to be applied to the sleep transistor; and 
 a controller, while the logic component is in sleep mode, configured to receive the negative voltage and determine whether to generate a control signal to adjust the negative voltage based on a comparison of a first current and a second current, the controller including:
 i) a first emulated sleep transistor configured to receive the negative voltage that defines produces the first current through the first emulated sleep transistor and create a first voltage drop at a drain of the first emulated sleep transistor; 
 ii) a second emulated sleep transistor configured to receive the negative voltage plus an offset voltage that define produce the second current through the second emulated sleep transistor and create a second voltage drop at a drain of the second emulated sleep transistor; and 
 iii) circuitry configured to effectively compare the first current to the second current based on a comparison of the first voltage drop and the second voltage drop. 
 
 
     
     
       17. The integrated circuit of  claim 16  wherein the first and second transistors are emulated sleep transistors. 
     
     
       18. The integrated circuit of  claim 17  wherein the voltage generator is configured to selectively generate the negative voltage. 
     
     
       19. The integrated circuit of  claim 16  wherein the controller is configured to continuously determine whether to adjust the negative voltage. 
     
     
       20. The integrated circuit of  claim 16  wherein the controller is configured to periodically determine whether to adjust the negative voltage. 
     
     
       21. The integrated circuit of  claim 16  wherein the voltage generator is configured to selectively generate the negative voltage. 
     
     
       22. The integrated circuit of  claim 21  wherein the voltage generator is a charge pump. 
     
     
       23. The integrated circuit of  claim 16  wherein the voltage generator is a charge pump. 
     
     
       24. An integrated circuit comprising:
 a logic component, the logic component being either a logic gate or a storage cell;   a sleep transistor coupled in series to the logic component and to a ground terminal;   a voltage generator configured to generate a negative voltage to be applied to the sleep transistor; and   controller circuitry configured to, while the logic component is in a standby mode:
 i) monitor a parameter of an emulated sleep transistor, the parameter of the emulated sleep transistor indicating static leakage of the logic component; 
 ii) generate a control signal for adjusting the negative voltage to be applied to the sleep transistor based on the parameter of the emulated sleep transistor, thereby reducing static leakage of the integrated circuit. 
   
     
     
       25. The integrated circuit of claim 24, wherein the emulated sleep transistor is an NMOS transistor. 
     
     
       26. The integrated circuit of claim 24, wherein the controller circuitry is further configured to continuously make determinations of whether to adjust the negative voltage to reduce the static leakage of the integrated circuit based on the parameter of the emulated sleep transistor. 
     
     
       27. The integrated circuit of claim 24, wherein the controller circuitry is configured to periodically make determinations of whether to adjust the negative voltage to reduce the static leakage of the integrated circuit. 
     
     
       28. The integrated circuit of claim 24, wherein the voltage generator is a charge pump.