Multi-chip package and memory system

Abstract

A multi-chip package includes a first group of memory chips that includes a first memory chip and a second memory chip, a second group of memory chips that includes at least one memory chip, a first internal wiring system that couples the first memory chip and the second memory chip to a first terminal configured to receive a chip-enable signal, a second internal wiring system that couples the at least one memory chip to a second terminal configured to receive the chip-enable signal. The first memory chip and the second memory chip each include a chip address memory region configured to store an address associated with the memory chip, and an address rewrite module configured to rewrite the address associated with the memory chip and stored in the chip address memory region in response to an external operation.

What is claimed: 
     
       1. A memory system comprising:
 a first memory chip in a multi-chip package; 
 a second memory chip in the multi-chip package; 
 a first internal wiring within the multi-chip package and that couples the first memory chip to a first terminal on the multi-chip package through which a first chip-enable signal is received; and 
 a second internal wiring within the multi-chip package and that couples the second memory chip to a second terminal on the multi-chip package through which a second chip-enable signal is received, 
 wherein the first memory chip comprises a chip address memory region configured to store an initial address for the first memory chip, an initial value-setting module configured to set the initial address in the chip address memory region, and a write rewrite module configured to write the a different address from the initial address into the chip address memory region based on an external operation addressed to the initial address. 
 
     
     
       2. The memory system according to  claim 1 , wherein the first memory chip includes an initial value-setting module configured to set the address associated with the memory chip to an initial state. 
     
     
       3. The memory system according to  claim 2 , wherein the first memory chip includes address-setting pins and the initial value-setting module is configured to set the initial state of the address based on voltages applied to the address-setting pins. 
     
     
       4. The memory system according to  claim 3 , wherein one of the address-setting pins is configured to couple the memory chip to a supply voltage and another of the address-setting pins is configured to be coupled to a ground voltage. 
     
     
       5. The memory system according to claim  2  1, wherein the chip address memory region includes a nonvolatile memory and the initial value-setting module is configured to set the initial state of the address based on a value stored in the nonvolatile memory. 
     
     
       6. The memory system according to  claim 1 , wherein the first terminal is configured to couple the first memory chip to a transfer controller. 
     
     
       7. The memory system according to  claim 6 , wherein the first terminal and the second terminal are electrically coupled to each other outside of the multi-chip package so that the first memory chip and the second memory chip are each configured to receive the same a common chip-enable signal. 
     
     
       8. The memory system according to  claim 6 , wherein the first terminal and the second terminal are independently coupled to the transfer controller of the memory system so that the first memory chip and the second memory chip each receive separate chip-enable signals. 
     
     
       9. The memory system according to  claim 1 , wherein the first internal wiring includes at least one of an input/output signal line, a control signal line, and a ready/busy signal line. 
     
     
       10. A memory system comprising:
 a first memory in a multi-chip package and connected to a first terminal of the multi-chip package through which a chip-enable signal is received; and 
 a second memory in the multi-chip package and connected to a second terminal of the multi-chip package through which a chip-enable signal is received, the first and second terminals being separate terminals of the multi-chip package,  
 wherein chip identification information for the first memory is set in a memory region of the first memory at a start up, and the chip identification information for the first memory is written into a in the memory region of the first memory from an initial state to a different state after the start up based on an external operation addressed to the first memory using the chip identification information of the initial state. 
 
     
     
       11. A memory system, comprising:
 a controller mounted on a circuit board;   a memory package mounted on the circuit board and including:
 a first memory chip including a first non-volatile memory cell array, 
 a second memory chip including a second non-volatile memory cell array, and 
 a plurality of external terminals including a first terminal electrically connected to the first memory chip by a first internal wiring, a second terminal electrically connected to the first memory chip by a second internal wiring, a third terminal electrically connected to the second memory chip by a third internal wiring, and a fourth terminal electrically connected to the second memory chip by a fourth internal wiring; 
   a plurality of board-side terminals on the circuit board and including a first board-side terminal connected to the first terminal, a second board-side terminal connected to the second terminal, a third board-side terminal connected to the third terminal, and a fourth board-side terminal connected to the fourth terminal; and   a plurality of signal lines on the circuit board and connecting the controller to the plurality of board-side terminals, the plurality of signal lines including a first signal line electrically connected to the first terminal, a second signal line electrically connected to the second terminal, a third signal line electrically connected to the third terminal, a fourth signal line electrically connected to the fourth terminal, wherein   the controller is configured to output a command to at least one of the first signal line and the third signal line and assert a chip enable signal on the second signal line and fourth signal line, the first memory chip being configured to perform in accordance with the command if an address associated with the command matches first address information established in the first memory chip and the chip enable signal is asserted, wherein   the first address information distinguishes the first memory chip from the second memory chip, and   the first and third signal lines are electrically connected to each other by a connection on the circuit board.    
     
     
       12. The memory system of claim 11, wherein the first, second, third, and fourth internal wirings are each a bonding wire.  
     
     
       13. The memory system of claim 11, wherein the memory package is mounted on the circuit board by solder.  
     
     
       14. The memory system of claim 11, wherein the first and second memory chips are stacked on each other in the memory package.