Vertical memory devices and methods of manufacturing the same

Abstract

A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a first direction that is vertical to a top surface of the substrate, a plurality of gate lines stacked on top of each other on the substrate, a plurality of wiring over the gate lines and electrically connected to the gate lines, and an identification pattern on the substrate at the same level as a level of at least one of the rings. The gate lines surround the channels. The gate lines are spaced apart from each other along the first direction.

What is claimed is: 
     
       1. A vertical memory device, comprising:
 a substrate; 
 a plurality of cell blocks on the substrate, each of the cell blocks including,
 a plurality of channels extending in a first direction vertical to a top surface of the substrate, 
 a plurality of gate lines stacked on top of each other on the substrate, the gate lines surrounding the channels, the gate lines being spaced apart from each other along the first direction; and 
 
 a plurality of wirings over the gate lines and electrically connected to the gate lines; and 
 an identification pattern on the substrate, the identification pattern corresponding to at least one of the plurality of the cell blocks, wherein 
 the identification pattern is at a same level above the substrate as a level of at least one of the wirings. 
 
     
     
       2. The vertical memory device of  claim 1 , wherein the identification pattern is at a same level above the substrate as a level of at least one of the wirings. 
     
     
       3. The vertical memory device of  claim 1 , wherein
 the gate lines extend in a second direction parallel to the top surface of the substrate, 
 the plurality of the cell blocks are spaced apart from each other along a third direction that is parallel to the top surface of the substrate, and 
 the third direction crosses the second direction. 
 
     
     
       4. The vertical memory device of  claim 1 , A vertical memory device, comprising:
 a substrate; 
 a plurality of cell blocks on the substrate, each of the cell blocks including,
 a plurality of channels extending in a first direction vertical to a top surface of the substrate, 
 a plurality of gate lines stacked on top of each other on the substrate, the gate lines surrounding the channels, the gate lines being spaced apart from each other along the first direction; and 
 a plurality of wirings over the gate lines and electrically connected to the gate lines; and 
 
 an identification pattern on the substrate, the identification pattern corresponding to at least one of the plurality of the cell blocks,  
 wherein at least one of the cell blocks further includes dummy wirings adjacent to the wirings. 
 
     
     
       5. The vertical memory device of  claim 3 , further comprising:
 a cutting pattern on the substrate between the cell blocks. 
 
     
     
       6. The vertical memory device of  claim 3 , further comprising:
 a plurality of block groups on the substrate and arranged in the third direction, wherein 
 each of the block groups include a group of the cell blocks. 
 
     
     
       7. The vertical memory device of  claim 5 , wherein
 the substrate includes a cell region and an extension region, 
 the channels are on the cell region, 
 end portions of the gate lines are on the extension region, and 
 the cutting pattern extends over the cell region and the extension region. 
 
     
     
       8. The vertical memory device of  claim 6 , further comprising:
 a plurality of identification patterns on the substrate, wherein 
 the identification patterns include the identification pattern, 
 the identification patterns are in each of the block groups. 
 
     
     
       9. The vertical memory device of  claim 7 , wherein the cutting pattern is a common source line. 
     
     
       10. The vertical memory device of  claim 4 , wherein a dummy wiring included in a cell block of the cell blocks in which the identification pattern is provided has a different shape from those of remaining dummy wirings of the dummy wirings. 
     
     
       11. A vertical memory device, comprising:
 a substrate; 
 a plurality of cell blocks on the substrate, each of the cell blocks including,
 a plurality of channels extending in a first direction vertical to a top surface of the substrate, 
 a plurality of gate lines stacked on top of each other on the substrate, the gate lines surrounding the channels, the gate lines being spaced apart from each other along the first direction; and 
 
 a plurality of wirings over the gate lines and electrically connected to the gate lines; and 
 an identification pattern on the substrate, the identification pattern corresponding to at least one of the plurality of the cell blocks and having a shape of a number or a Roman alphabet The vertical memory device of claim 1, wherein the identification pattern has a shape of a number or a Roman alphabet. 
 
     
     
       12. A vertical memory device, comprising:
 a substrate including a cell region and an extension region;   cell blocks on the substrate, each of the cell blocks including,
 channels extending on the cell region of the substrate in a first direction vertical to a top surface of the substrate, 
 gate lines stacked on top of each other on the cell region and the extension region of the substrate, the gate lines surrounding the channels, the gate lines being spaced apart from each other along the first direction, and end portions of the gate lines being on the extension region of the substrate, and 
 wirings over the gate lines and electrically connected to the gate lines; 
   cutting patterns extending in a second direction parallel to the top surface of the substrate from the cell region to the extension region of the substrate, the cutting patterns including a metal, and the metal extending in the first direction to the substrate; and   an identification pattern on the substrate, the identification pattern corresponding to at least one of the cell blocks, wherein   the cell blocks are spaced apart from each other by the cutting patterns,   the identification pattern is disposed between neighboring ones of the cutting patterns in a plan view, and   the identification pattern is at a same level above the substrate as a level of at least one of the wirings.    
     
     
       13. The vertical memory device of claim 12, wherein
 the gate lines extend in the second direction,   the cell blocks are spaced apart from each other along a third direction that is parallel to the top surface of the substrate, and   the third direction crosses the second direction.    
     
     
       14. The vertical memory device of claim 13, further comprising:
 a bit line extending in the third direction on the substrate, the bit line being electrically connected to at least one of the channels.    
     
     
       15. The vertical memory device of claim 14, wherein the identification pattern is disposed in an area defined by the neighboring ones of the cutting patterns extending in the second direction, the bit line extending in the third direction, and the at least one of the wirings, in a plan view.  
     
     
       16. The vertical memory device of claim 14, wherein the identification pattern and the bit line are at the same level.  
     
     
       17. The vertical memory device of claim 12, wherein the identification pattern is at a same level above the substrate as a level of a lowermost one of the wirings.  
     
     
       18. The vertical memory device of claim 12, further comprising contacts connected to the end portions of the gate lines, respectively, on the extension region of the substrate,
 wherein the wirings are electrically connected to the gate lines via the contacts.    
     
     
       19. The vertical memory device of claim 12, wherein the gate lines include step portions arranged on the extension region of the substrate, and wherein the identification pattern is disposed between the cell region and the extension region of the substrate.  
     
     
       20. The vertical memory device of claim 12, wherein the identification pattern has a shape of a number.