Semiconductor integrated circuit

Abstract

A semiconductor integrated circuit able to reduce a load of layout design when arranging switches in a power lines for preventing leakage current and able to reduce the influence of a voltage drop occurring in the switches on a signal delay, wherein a plurality of groups of power lines are arranged in stripe shapes, power is supplied to circuit cells by a plurality of groups of branch lines branching from the groups of power lines, power switch cells arranged in the groups of branch lines turn on or off the supply of power to the circuit cells, the power switch cells are arranged dispersed in the area of arrangement of the circuit cells, and the supply of power by the power switch cells is finely controlled for every relatively small number of circuit cells.

The invention claimed is: 
     
       1. A semiconductor integrated circuit comprising:
 a first branch line adapted to provide a potential to a first circuit cell, a power line being at said potential;   a second branch line adapted to provide said potential to a second circuit cell; and   a third branch line adapted to provide another potential to said first and second circuit cells, another power line being at said another potential,   wherein an electrical connection between said first branch line and said power line is controlled in accordance with a state of a control signal.   
     
     
       2. A semiconductor integrated circuit as set forth in  claim 1 , wherein said first circuit cell and said second circuit cell can be arranged mixed at any positions on said first and second branch lines. 
     
     
       3. A semiconductor integrated circuit as set forth in  claim 1 , wherein said potential is VSS. 
     
     
       4. A semiconductor integrated circuit as set forth in  claim 1 , wherein an interconnection between said power line and said second branch line is present regardless of said state of the control signal. 
     
     
       5. A semiconductor integrated circuit as set forth in  claim 1 , wherein said another potential is VDD. 
     
     
       6. A semiconductor integrated circuit as set forth in  claim 1 , wherein said third branch line connects said another power line to said first and second circuit cells regardless of said state of the control signal. 
     
     
       7. A semiconductor integrated circuit as set forth in  claim 1 , further comprising:
 a power switch cell adapted to control said electrical connection between said first branch line and said power line.   
     
     
       8. A semiconductor integrated circuit as set forth in  claim 7 , wherein said power switch cell comprises:
 a first interconnect line connected to said first branch line;   a second interconnect line connected to said power line; and   a switch circuit between said first interconnect line and said second interconnect line connecting said first interconnect line to said second interconnect line in accordance with said state of the control signal.   
     
     
       9. A semiconductor integrated circuit comprising:
 a first power line configured to receive a first potential that differs from a second potential;   a second power line configured to receive the second potential when the first power line receives the first potential;   a first branch line electrically connected to a first circuit cell so that, when a power switch cell electrically connects the first power line to the first branch line, the first branch line supplies the first potential from the first power line to the first circuit cell;   a second branch line electrically connected to a second circuit cell so that, when the power switch cell electrically disconnects the first power line from the first branch line, the second branch line continues to supply the first potential from the first power line to the second circuit cell; and   a third branch line electrically connected to the first circuit cell and the second circuit cell so that, when the power switch cell electrically disconnects the first power line from the first branch line, the third branch line continues to supply the second potential from the second power line to the first circuit cell and the second circuit cell.   
     
     
       10. A semiconductor integrated circuit as set forth in claim 9, wherein the first potential is VSS. 
     
     
       11. A semiconductor integrated circuit as set forth in claim 9, wherein the second potential is VDD. 
     
     
       12. A semiconductor integrated circuit as set forth in claim 9, wherein the first power line is in parallel with the second power line. 
     
     
       13. A semiconductor integrated circuit as set forth in claim 9, wherein the first power line is perpendicular to the first branch line. 
     
     
       14. A semiconductor integrated circuit as set forth in claim 9, wherein the first branch line is between the second power line and the third branch line. 
     
     
       15. A semiconductor integrated circuit as set forth in claim 9, wherein the first branch line is in parallel with the second branch line. 
     
     
       16. A semiconductor integrated circuit as set forth in claim 9, wherein the first branch line is in parallel with the third branch line. 
     
     
       17. A semiconductor integrated circuit as set forth in claim 9, wherein the second branch line is in parallel with the third branch line. 
     
     
       18. A semiconductor integrated circuit as set forth in claim 9, wherein when the power switch cell electrically disconnects the first power line from the first branch line, the power switch cell obstructs the first branch line from supplying the first potential from the first power line to the first circuit cell. 
     
     
       19. A semiconductor integrated circuit as set forth in claim 9, wherein when the power switch cell electrically connects the first power line to the first branch line, the second branch line continues to supply the first potential from the first power line to the second circuit cell. 
     
     
       20. A semiconductor integrated circuit as set forth in claim 9, wherein when the power switch cell electrically connects the first power line to the first branch line, the third branch line to continues to supply the second potential from the second power line to the first circuit cell and the second circuit cell. 
     
     
       21. A semiconductor integrated circuit as set forth in claim 9, wherein when the power switch cell electrically connects the first power line to the first branch line, the second branch line remains electrically connected to the second circuit cell in the manner that permits the second branch line to supply the first potential from the first power line to the second circuit cell. 
     
     
       22. A semiconductor integrated circuit as set forth in claim 9, wherein when the power switch cell electrically connects the first power line to the first branch line, the third branch line remains electrically connected to the first circuit cell and the second circuit cell in the manner that permits the third branch line to supply the second potential from the second power line to the first circuit cell and the second circuit cell.