Driving circuit of a liquid crystal display panel

Abstract

A driving circuit of a liquid crystal display panel includes a substrate, a plurality of driver IC chips located on the substrate, a current supplier, and a first conductive wire set. The first conductive wire set has a plurality of conductive wire segments for connecting the driver IC chips in parallel to the current supplier. Furthermore, the conductive wire segments each have a form, such that paths formed of the conductive wire segments from the current supplier to the respective driver IC chips have an equal resistance, and, accordingly, each of the driver IC chips obtain the same input voltage. Hence, a problem of band mura is avoided.

What is claimed is: 
     
       1. A driving circuit of a liquid crystal display panel, comprising:
 a substrate;   a plurality of driver IC chips positioned on the substrate;   a current supplier; and   a first conductive wire set comprising a conductive wire for electrically connecting the driver IC chips in parallel to the current supplier.   
     
     
       2. The driving circuit of  claim 1 , wherein the conductive wire and the driver IC chips are electrically connected by a plurality of conductive wire segments, and the conductive wire segments each have a form, such that paths formed of the conductive wire segments from the current supplier to the respective driver IC chips each have an equal resistance and each of the driver IC chips obtain a same input voltage. 
     
     
       3. The driving circuit of  claim 1 , wherein the first conductive wire set comprises a metal layer, alloy layer, or indium tin oxide (ITO) layer. 
     
     
       4. The driving circuit of  claim 1 , wherein the substrate further comprises a plurality of scanning lines and a plurality of signal lines. 
     
     
       5. The driving circuit of  claim 4 , wherein the driver IC chips output switch/addressing signals to the scanning lines. 
     
     
       6. The driving circuit of  claim 4 , wherein the driver IC chips output image information signals to the signal lines. 
     
     
       7. The driving circuit of  claim 4 , wherein the first conductive wire set comprises a same material as the scanning lines. 
     
     
       8. The driving circuit of  claim 4 , wherein the first conductive wire set comprises a same material as the signal lines. 
     
     
       9. The driving circuit of  claim 1 , further comprises a second conductive wire set comprising a conductive wire for electrically connecting the driver IC chips in parallel to the current supplier. 
     
     
       10. The driving circuit of  claim 9 , wherein the conductive wire included in the second conductive wire set and each of the driver IC chips are electrically connected by a conductive wire segment, and the conductive wire segments each have a form, such that paths formed of the second conductive wire segments from the current supplier to the respective driver IC chips have an equal resistance and each of the driver IC chips obtain a same input voltage. 
     
     
       11. The driving circuit of  claim 9 , wherein the first conductive wire set carries a thin film transistor on-state current and the second conductive wire set carries a thin film transistor off-state current. 
     
     
       12. The driving circuit of  claim 9 , wherein the second conductive wire set comprises a metal layer, alloy layer, or indium tin oxide (ITO) layer. 
     
     
       13. The driving circuit of  claim 9 , wherein the substrate further comprises a plurality of scanning lines and a plurality of signal lines. 
     
     
       14. The driving circuit of  claim 13 , wherein the driver IC chips output switch/addressing signals to the scanning lines. 
     
     
       15. The driving circuit of  claim 13 , wherein the driver IC chips output image information signals to the signal lines. 
     
     
       16. The driving circuit of  claim 13 , wherein the second conductive wire set comprises a same material as the scanning lines. 
     
     
       17. The driving circuit of  claim 13 , wherein the second conductive wire set comprises a same material as the signal lines. 
     
     
       18. A method of fabricating a driving circuit of a liquid crystal display panel, the method comprising:
 forming a first driver IC chip and a second driver IC chip on a substrate, wherein the first driver IC chip and the second driver IC chip are configured to drive scanning lines of the display panel;   forming a first electrical connection from the first driver IC chip to a current supplier, wherein at least a portion of the first electrical connection is formed on the substrate; and   forming a second electrical connection from the second driver IC chip to the current supplier, wherein at least a portion of the second electrical connection is formed on the substrate;   wherein the first driver IC chip and a second driver IC chip are electrically connected in parallel to the current supplier via the first and second electrical connections,   wherein the first electrical connection has a first electrical resistance through first conductive wire segments from the current supplier to the first driver IC chip, and the second electrical connection has a second electrical resistance through second conductive wire segments from the current supplier to the second driver IC chip,   wherein the first conductive wire segments and the second conductive wire segments comprise: common segments, first separate segments of the first conductive wire segments, and second separate segments of the second conductive wire segments, wherein the first separate segments have a first cross-section and wherein the second separate segments have a second cross-section that is different from the first cross-section, and   wherein the first electrical resistance is substantially the same as the second electrical resistance.    
     
     
       19. The method of claim 18, wherein the first electrical connection is configured to provide the first driver IC chip with an input voltage and the second electrical connection is configured to provide the second driver IC chip with substantially the same input voltage.  
     
     
       20. The method of claim 18, further comprising:
 fabricating a plurality of scanning lines on the substrate; and   fabricating a plurality of signal lines on the substrate.    
     
     
       21. The method of claim 20, wherein the first and second electrical connections comprise a material and the plurality of scanning lines comprise the same material.  
     
     
       22. The method of claim 21, wherein the first and second electrical connections are formed and the plurality of scanning lines are fabricated substantially simultaneously.  
     
     
       23. The method of claim 18, wherein the first driver IC chip and the second driver IC chip are formed on the substrate using a chip-on-glass process.  
     
     
       24. The method of claim 18, further comprising:
 forming a third electrical connection from the first driver IC chip to the current supplier, wherein at least a portion of the third electrical connection is formed on the substrate; and   forming a fourth electrical connection from the second driver IC chip to the current supplier, wherein at least a portion of the second electrical connection is formed on the substrate.    
     
     
       25. The method of claim 24, wherein:
 the first electrical connection is configured to provide the first driver IC chip with a first input voltage;   the second electrical connection is configured to provide the second driver IC chip with substantially the same first input voltage;   the third electrical connection is configured to provide the first driver IC chip with a second input voltage; and   the fourth electrical connection is configured to provide the second driver IC chip with substantially the same second input voltage.    
     
     
       26. The method of claim 24, wherein:
 the first electrical connection has a first electrical resistance;   the second electrical connection has substantially the same first electrical resistance;   the third electrical connection has a second electrical resistance; and   the fourth electrical connection has substantially the same second electrical resistance.    
     
     
       27. The method of claim 24, wherein the first and second electrical connections are configured to carry a thin film transistor on-state current and the third and fourth electrical connections are configured to carry a thin film transistor off-state current.  
     
     
       28. The method of claim 18, wherein the substrate is substantially rectangular and the first driver IC chip is arranged along one edge of the substrate and the second driver IC chip is arranged along the same edge of the substrate.