Semiconductor integrated circuit

Abstract

Disclosed herein is a semiconductor integrated circuit, wherein a desired circuit is formed by combining and laying out a plurality of standard cells and connecting the cells together, of which the cell length, i.e., the gap between a pair of opposed sides, is standardized, the plurality of standard cells forming the desired circuit include complementary in-phase driven standard cells, each of which includes a plurality of complementary transistor pairs that are complementary in conductivity type to each other and have their gate electrodes connected together, and N (≥2) pairs of all the complementary transistor pairs are driven in phase, and the size of the standardized cell length of the complementary in-phase driven standard cell is defined as an M-fold cell length which is M (N≥M≥2) times the basic cell length which is appropriate to the single complementary transistor pair.

What is claimed is: 
     
       1. A semiconductor integrated circuit, wherein
 a desired circuit is formed by combining and laying out plurality of standard cells and connecting the cells together, of which the cell length, i.e., the gap between a pair of opposed sides, is standardized,   the plurality of standard cells forming the desired circuit include complementary in-phase driven standard cells, each of which includes a plurality of complementary transistor pairs that are complementary in conductivity type to each other and have their gate electrodes connected together, and N (≥2) pairs of all the complementary transistor pairs are driven in phase, and   the size of the standardized cell length of the complementary in-phase driven standard cell is defined as an M-fold cell length which is M (N≥M≥2) times the basic cell length which is appropriate to the single complementary transistor pair, and the common gate electrodes of at least M pairs of the N complementary transistor pairs to be driven in phase are arranged linearly in the direction of the M-fold cell length.   
     
     
       2. The semiconductor integrated circuit of  claim 1 , wherein
 single height cells or standard cells having the basic cell length and multi-height cells or the complementary in-phase driven standard cells having the M-fold cell length are arranged adjacent to each other to share power lines so as to form the desired circuit.   
     
     
       3. The semiconductor integrated circuit of  claim 2 , wherein
 the multi-height cell has a total of (M+1) power lines which is the sum of (M−1) power wirings that are arranged parallel to each other to extend in an arbitrary cell length direction orthogonal to the M-fold cell length with a separation pitch equal to the basic cell length obtained by dividing the M-fold cell length into M equal parts and two shared power wirings, each of which is shared with an adjacent cell at the center of the width of one of two cell boundaries, one on each side along the M-fold cell length,   the (M+1) power lines include source voltage lines and reference voltage lines that are alternately arranged, and   the single height cell connected to a pair of the source voltage line and reference voltage line arranged adjacent and parallel to each other is arranged adjacent to the multi-height cell in the arbitrary cell length direction.   
     
     
       4. The semiconductor integrated circuit of  claim 3 , wherein
 two active regions of the same conductivity type where transistors are respectively formed are arranged line-symmetrically with respect to the center line of the width of each of the (M−1) power wirings, and   the common gate electrodes are arranged linearly to intersect each of one of the active regions, power wirings and the other of the active regions.   
     
     
       5. The semiconductor integrated circuit of  claim 4 , wherein
 all the gate electrodes overlapping an element isolation region provided between the two active regions are the common gate electrodes extending from one of the two active regions to the other of the two active regions and intersecting the element isolation region.   
     
     
       6. The semiconductor integrated circuit of  claim 3 , wherein
 the (M+1) power lines and all intracell connection lines are formed with a first metal wiring layer, and   intercell signal lines are formed with a second metal wiring layer.   
     
     
       7. The semiconductor integrated circuit of  claim 2 , wherein
 the multi-height cell is a non-rectangular cell that surrounds the single height cell in an L-shaped manner by including first and second rectangular sections, the first rectangular section having the M-fold cell length in which M complementary transistor pairs of all the complementary transistor pairs to be driven in phase are arranged, and the second rectangular section extending along one of two sides that are opposed to each other in the direction of the standardized cell length of the first rectangular section.   
     
     
       8. The semiconductor integrated circuit of  claim 1 , wherein
 a plurality of standard cells forming the desired circuit include at least one non-rectangular standard cell that is L-shaped as a whole in plan view by comprising first and second rectangular sections, the first rectangular section having the M-fold cell length in which M complementary transistor pairs of all the complementary transistor pairs to be driven in phase are arranged, and the second rectangular section extending along one of two sides that are opposed to each other in the direction of the standardized cell length of the first rectangular section.   
     
     
       9. A semiconductor integrated circuit comprising:
 first voltage lines that extend in a first direction, the first direction differs from a second direction;   second voltage lines that extend in the first direction, one of the second voltage lines is between one of the first voltage lines and a different one of the first voltage lines; and   a multi-height standard cell comprising:
 a first region including a first active region of a first conductivity type, the first conductivity type differs from a second conductivity type, 
 a second region including a second active region of the second conductivity type, the first region and the second region are between the one of the first voltage lines and the one of the second voltage lines, 
 a third region including a third active region of the first conductivity type, 
 a fourth region including a fourth active region of the second conductivity type, the third region and the fourth region are between the one of the second voltage lines and the different one of the first voltage lines, 
 an element isolation region located between at least any two regions selected from the first region, second region, third region and the fourth region, 
 a first gate electrode configured to drive a first plurality of complementary transistor pairs, 
 a second gate electrode configured to drive a second plurality of complementary transistor pairs, and 
 a third gate electrode that is shorter than the first gate electrode, 
   wherein:
 the first gate electrode and the second gate electrode have a straight linear shape in a gate layer, 
 the first gate electrode and the second gate electrode extends in the multi-height standard cell along the second direction while overlapping at least the first region, the second region, the third region and the fourth region, and 
 the third gate electrode extends in the multi-height standard cell along the second direction while overlapping at least the first region and the second region, 
   wherein a cell length of the multi-height standard cell is:
 a distance in the second direction from a center of the one of the first voltage lines to a center of the different one of the first voltage lines, and 
 M (M≥2) times a distance between the center of the one of the first voltage lines and a center of the one of the second voltage lines. 
   
     
     
       10. The semiconductor integrated circuit as set forth in claim 9, wherein
 the third gate electrode extends in the multi-height standard cell along the second direction while overlapping at least the first region and the second region but not overlapping the third region and the fourth region.   
     
     
       11. The semiconductor integrated circuit as set forth in claim 10, wherein
 the second gate electrode is configured to receive a signal from an outside of the multi-height standard cell.   
     
     
       12. The semiconductor integrated circuit as set forth in claim 11, wherein
 a first complementary transistor pair comprising the third gate electrode is configured to output a first output signal.   
     
     
       13. The semiconductor integrated circuit as set forth in claim 12, further comprising:
 a first internal wiring in a wiring layer,   wherein:
 the first internal wiring is located in the multi-height standard cell, and 
 the first internal wiring intersects the first gate electrode. 
   
     
     
       14. The semiconductor integrated circuit as set forth in claim 13, wherein
 the first internal wiring intersects the second gate electrode.   
     
     
       15. The semiconductor integrated circuit as set forth in claim 13, wherein
 the first internal wiring is configured to deliver an intracell signal.   
     
     
       16. The semiconductor integrated circuit as set forth in claim 15, further comprising:
 a first transistor in the third region,   wherein the first transistor is configured to output the intracell signal.   
     
     
       17. The semiconductor integrated circuit as set forth in claim 16, further comprising:
 a fourth gate electrode configured to receive the intracell signal,   wherein:
 the second gate electrode is between the first gate electrode and the fourth gate electrode, and 
 the first internal wiring connects to the fourth gate electrode. 
   
     
     
       18. The semiconductor integrated circuit as set forth in claim 17, wherein
 the fourth gate electrode is configured to drive a third plurality of complementary transistor pairs,   the fourth gate electrode extends in the multi-height standard cell along the second direction while overlapping at least the first region, the second region, the third region and the fourth region, and   the fourth gate electrode has a straight linear shape in the gate layer.   
     
     
       19. The semiconductor integrated circuit as set forth in claim 18, wherein
 the third gate electrode is shorter than the fourth gate electrode.   
     
     
       20. The semiconductor integrated circuit as set forth in claim 19, wherein
 the third gate electrode is positioned right side from the first gate electrode, the second gate electrode and the fourth gate electrode.   
     
     
       21. The semiconductor integrated circuit as set forth in claim 12, further comprising:
 a fourth gate electrode configured to drive a third plurality of complementary transistor pairs,   wherein:
 the fourth gate electrode extends in the multi-height standard cell along the second direction while overlapping at least the first region, the second region, the third region and the fourth region, and 
 the fourth gate electrode has a straight linear shape in the gate layer. 
   
     
     
       22. The semiconductor integrated circuit as set forth in claim 21, wherein
 the first gate electrode, the second gate electrode and the fourth gate electrode are positioned in order from left to right.   
     
     
       23. The semiconductor integrated circuit as set forth in claim 22, wherein
 the third gate electrode is positioned right side from the first gate electrode, the second gate electrode and the fourth gate electrode.   
     
     
       24. The semiconductor integrated circuit as set forth in claim 12, further comprising:
 a second internal wiring in a wiring layer,   wherein the second internal wiring is configured to deliver the first output signal to the outside of the multi-height standard cell.   
     
     
       25. The semiconductor integrated circuit as set forth in claim 24, further comprising:
 a third internal wiring in the wiring layer,   wherein:
 the third internal wiring is configured to deliver a second output signal to the outside of the multi-height standard cell, and 
 the second output signal is configured to be different from the first output signal. 
   
     
     
       26. The semiconductor integrated circuit as set forth in claim 25, wherein
 the second internal wiring extends in the multi-height standard cell along the second direction while overlapping at least the first region and the second region, and   the third internal wiring extends in the multi-height standard cell along the second direction while overlapping at least the third region and the fourth region.   
     
     
       27. The semiconductor integrated circuit as set forth in claim 9, wherein
 the first region consists of the first active region of the first conductivity type,   the second region consists of the second active region of the second conductivity type,   the third region consists of the third active region of the first conductivity type, and   the fourth region consists of the fourth active region of the second conductivity type.   
     
     
       28. The semiconductor integrated circuit as set forth in claim 27, wherein
 the third active region continuously extends in the first direction.   
     
     
       29. The semiconductor integrated circuit as set forth in claim 26, further comprising:
 a single height standard cell, a cell length of the single height standard cell is a distance in the second direction from the one of the second voltage lines to the one of the first voltage lines.   
     
     
       30. The semiconductor integrated circuit as set forth in claim 29, wherein
 the cell length of the multi-height standard cell is double of the cell length of the single height standard cell.   
     
     
       31. The semiconductor integrated circuit as set forth in claim 26, further comprising:
 a branch line extending from the one of the second voltage lines.   
     
     
       32. The semiconductor integrated circuit as set forth in claim 31, wherein
 the second internal wiring, the third internal wiring and the branch line are located in a first metal layer of the wiring layer.   
     
     
       33. The semiconductor integrated circuit as set forth in claim 32, wherein
 the first voltage lines and the second voltage lines are located in the first metal layer of the wiring layer.   
     
     
       34. The semiconductor integrated circuit as set forth in claim 26, wherein
 the first gate electrode is configured to drive at least part of a first logic circuit and at least part of a second logic circuit.   
     
     
       35. The semiconductor integrated circuit as set forth in claim 34, wherein
 the first logic circuit is a NAND circuit, and   the second circuit is an inverter circuit.   
     
     
       36. The semiconductor integrated circuit as set forth in claim 16, further comprising:
 a second transistor in the fourth region,   wherein the first transistor and the second transistor are configured to output the intracell signal.   
     
     
       37. The semiconductor integrated circuit as set forth in claim 26, wherein
 a length of the first gate electrode is same as a length of the second gate electrode.   
     
     
       38. The semiconductor integrated circuit as set forth in claim 26, wherein
 the second gate electrode is adjacent to the first gate electrode.