Video decoding system supporting multiple standards

Abstract

System and method for decoding digital video data. The decoding system employs hardware accelerators that assist a core processor in performing selected decoding tasks. The hardware accelerators are configurable to support a plurality of existing and future encoding/decoding formats. The accelerators are configurable to support substantially any existing or future encoding/decoding formats that fall into the general class of DCT-based, entropy decoded, block-motion-compensated compression algorithms. The hardware accelerators illustratively comprise a programmable entropy decoder, an inverse quantization module, a inverse discrete cosine transform module, a pixel filter, a motion compensation module and a de-blocking filter. The hardware accelerators function in a decoding pipeline wherein at any given stage in the pipeline, while a given function is being performed on a given macroblock, the next macroblock in the data stream is being worked on by the previous function in the pipeline.

What is claimed is: 
     
       1. A method of decoding a digital media data stream, comprising:
 (a) receiving media data of a first encoding/decoding format; 
 (b) configuring at least one external decoding function based on the first encoding/decoding format; 
 (c) decoding media data of the first encoding/decoding format using the at least one external decoding function; 
 (d) receiving media data of a second encoding/decoding format; 
 (e) configuring the at least one external decoding function based on the second encoding/decoding format; and 
 (f) decoding media data of the second encoding/decoding format using the at least one external decoding function,
 wherein decoding media data using the at least one external decoding function in operations (c) and (f) comprises at least one configurable hardware module performing the at least one external decoding function, and wherein configuring the at least one external decoding function in operations (b) and (e) comprises configuring the at least one configurable hardware module, 
 wherein the at least one configurable hardware module is a plurality of configurable hardware modules, and wherein each of the plurality of configurable hardware modules performs at least one decoding function, 
 wherein at least one of the plurality of configurable hardware modules does not include a processor. 
 
 
     
     
       2. The method of  claim 1 , wherein the digital media data stream is a video stream and the media data is video data. 
     
     
       3. The method of  claim 2 , wherein the at least one external decoding function is an entropy decoding function. 
     
     
       4. The method of  claim 2 , wherein the at least one external decoding function is an inverse quantization function. 
     
     
       5. The method of  claim 2 , wherein the at least one external decoding function is an inverse transform operation. 
     
     
       6. The method of  claim 2 , wherein the at least one external decoding function is a pixel filtering function. 
     
     
       7. The method of  claim 2 , wherein the at least one external decoding function is a motion compensation function. 
     
     
       8. The method of  claim 2 , wherein the at least one external decoding function is a de-blocking operation. 
     
     
       9. A video decoding method, comprising:
 receiving a first video macroblock encoded in a first encoding format;   configuring a first external decoding function based on the first encoding format;   decoding the first video macroblock using the first external decoding function;   receiving a second video macroblock encoded in a second encoding format;   configuring a second external decoding function based on the second encoding format; and   decoding the second video macroblock using the second external decoding function.   
     
     
       10. The method of  claim 9 , wherein the first external decoding function is an entropy decoding function. 
     
     
       11. The method of  claim 9 , wherein the first external decoding function is an inverse quantization function. 
     
     
       12. The method of  claim 9 , wherein the first external decoding function is an inverse transform operation. 
     
     
       13. The method of  claim 9 , wherein the first external decoding function is a pixel filtering function. 
     
     
       14. The method of  claim 9 , wherein the first external decoding function is a motion compensation function. 
     
     
       15. The method of  claim 9 , wherein the first external decoding function is a de-blocking operation. 
     
     
       16. The method of  claim 9 , wherein the second external decoding function is one selected from the group consisting of:
 an entropy decoding function;   an inverse quantization function;   an inverse transform operation;   a pixel filtering function;   a motion compensation function; and   a de-blocking operation.   
     
     
       17. A video decoding method, comprising:
 determining a data format for a video data stream;   configuring a programmable entropy decoder to perform entropy decoding based on the determined data format;   configuring an inverse quantizer to perform an inverse quantization based on the determined data format;   configuring an inverse transform accelerator to perform an inverse transform operations based on the determined data format;   configuring a pixel filter to perform a pixel filtering based on the determined data format;   configuring a motion compensator to perform a motion compensation based on the determined data format; and   configuring a de-blocking filter to perform a de-blocking operation based on the determined data format.   
     
     
       18. The method of  claim 17 , wherein the video data stream comprises a digital video image. 
     
     
       19. The method of  claim 18 , wherein the digital video image comprises macroblocks. 
     
     
       20. The method of  claim 17 , further comprising determining a second data format for a second video data stream; and configuring at least one of the programmable entropy decoder, inverse quantizer, inverse transform accelerator, pixel filter, motion compensator, and de-blocking filter to perform operations based on the determined second data format. 
     
     
       21. The method of claim 1, wherein the plurality of configurable hardware modules comprises two or more configurable hardware modules selected from the group consisting of:
 an inverse quantizer adapted to perform inverse quantization on the digital media data stream;   an inverse transform accelerator adapted to perform inverse transform operations on the digital media data stream;   a pixel filter adapted to perform pixel filtering on the digital media data stream;   a motion compensator adapted to perform motion compensation on the digital media data stream; and   a de-blocking filter adapted to perform a de-blocking operation on the digital media data stream.    
     
     
       22. The method of claim 1, wherein the plurality of configurable hardware modules comprises four or more configurable hardware modules selected from the group consisting of:
 an inverse quantizer adapted to perform inverse quantization on the digital media data stream;   an inverse transform accelerator adapted to perform inverse transform operations on the digital media data stream;   a pixel filter adapted to perform pixel filtering on the digital media data stream;   a motion compensator adapted to perform motion compensation on the digital media data stream; and   a de-blocking filter adapted to perform a de-blocking operation on the digital media data stream.    
     
     
       23. The method of claim 1, wherein the plurality of configurable hardware modules comprises:
 an inverse quantizer adapted to perform inverse quantization on the digital media data stream;   an inverse transform accelerator adapted to perform inverse transform operations on the digital media data stream;   a pixel filter adapted to perform pixel filtering on the digital media data stream;   a motion compensator adapted to perform motion compensation on the digital media data stream; and   a de-blocking filter adapted to perform a de-blocking operation on the digital media data stream.    
     
     
       24. The method of claim 1, wherein the plurality of configurable hardware modules comprises three or more configurable hardware modules selected from the group consisting of:
 an inverse quantizer adapted to perform inverse quantization on the digital media data stream;   an inverse transform accelerator adapted to perform inverse transform operations on the digital media data stream;   a pixel filter adapted to perform pixel filtering on the digital media data stream;   a motion compensator adapted to perform motion compensation on the digital media data stream; and   a de-blocking filter adapted to perform a de-blocking operation on the digital media data stream.    
     
     
       25. A method of decoding a digital media data stream, comprising:
 (a) receiving media data of a first encoding/decoding format;   (b) configuring at least one external decoding function based on the first encoding/decoding format;   (c) decoding media data of the first encoding/decoding format using the at least one external decoding function;   (d) receiving media data of a second encoding/decoding format;   (e) configuring the at least one external decoding function based on the second encoding/decoding format; and   (f) decoding media data of the second encoding/decoding format using the at least one external decoding function,
 wherein decoding media data using the at least one external decoding function in operations (c) and (f) comprises at least one configurable hardware module performing the at least one external decoding function, and wherein configuring the at least one external decoding function in operations (b) and (e) comprises configuring the at least one configurable hardware module, 
 wherein the at least one configurable hardware module is a plurality of configurable hardware modules, and wherein each of the plurality of configurable hardware modules performs at least one decoding function, 
 wherein none of the plurality of configurable hardware modules includes a processor.  
   
     
     
       26. The method of claim 24, wherein at least one of the plurality of configurable hardware modules is a hardware accelerator.  
     
     
       27. A method of decoding a digital media data stream, comprising:
 (a) receiving media data of a first encoding/decoding format;   (b) configuring at least one external decoding function based on the first encoding/decoding format;   (c) decoding media data of the first encoding/decoding format using the at least one external decoding function;   (d) receiving media data of a second encoding/decoding format;   (e) configuring the at least one external decoding function based on the second encoding/decoding format; and   (f) decoding media data of the second encoding/decoding format using the at least one external decoding function,
 wherein decoding media data using the at least one external decoding function in operations (c) and (f) comprises at least one configurable hardware module performing the at least one external decoding function, and wherein configuring the at least one external decoding function in operations (b) and (e) comprises configuring the at least one configurable hardware module, 
 wherein the at least one configurable hardware module is a plurality of configurable hardware modules, and wherein each of the plurality of configurable hardware modules performs at least one decoding function, 
 wherein each of the configurable hardware modules is separate from others of the plurality of configurable hardware modules.  
   
     
     
       28. The method of claim 24, wherein the plurality of configurable hardware modules runs in parallel according to a processing pipeline.  
     
     
       29. The method of claim 28, further comprising, dictating, by a core decoding processor, the processing pipeline.  
     
     
       30. The method of claim 24, wherein a core decoding processor programs a register for at least one of the configurable hardware modules.  
     
     
       31. A method of decoding a digital media data stream, comprising:
 (a) receiving media data of a first encoding/decoding format;   (b) configuring at least one external decoding function based on the first encoding/decoding format;   (c) decoding media data of the first encoding/decoding format using the at least one external decoding function;   (d) receiving media data of a second encoding/decoding format;   (e) configuring the at least one external decoding function based on the second encoding/decoding format; and   (f) decoding media data of the second encoding/decoding format using the at least one external decoding function,
 wherein decoding media data using the at least one external decoding function in operations (c) and (f) comprises at least one configurable hardware module performing the at least one external decoding function, and wherein configuring the at least one external decoding function in operations (b) and (e) comprises configuring the at least one configurable hardware module, 
 wherein the at least one configurable hardware module is a plurality of configurable hardware modules, and wherein each of the plurality of configurable hardware modules performs at least one decoding function, 
 wherein each of the plurality of configurable hardware modules is independently controlled by a core decoding processor, 
 wherein the core decoding processor independently controls each of the plurality of configurable hardware modules by programming a register for each of the plurality of configurable hardware modules.