Negative capacitance FinFET device and manufacturing method of the same

Abstract

Provided is a negative capacitance FinFET device including a FinFET device including a gate stack, a drain electrode and a source electrode formed on a substrate and a ferroelectric negative capacitor connected to the gate stack of the FinFET device and having a negative capacitance. The FinFET device has an extension length (Lext) from a side-wall of the gate stack to the drain electrode or the source electrode and the extension length is set such that a size of a hysteresis window in the negative capacitance FinFET device is 1 V or less.

We claim: 
     
       1. A negative capacitance FinFET device comprising:
 a FinFET device including a gate stack, a drain electrode and a source electrode formed on a substrate; and 
 a ferroelectric negative capacitor connected to the gate stack of the FinFET device and having a negative capacitance, 
 wherein the FinFET device has an extension length (L ext ) from a side-wall of the gate stack to the drain electrode or the source electrode, and 
 the extension length is set such that a size of a hysteresis window in the negative capacitance FinFET device is in a range from 0.4 V to 1 V or less. 
 
     
     
       2. The negative capacitance FinFET device of  claim 1 ,
 wherein the extension length is set to be in a range from 80 nm to 150 nm. . 
 
     
     
       3. The negative capacitance FinFET device of  claim 1 ,
 wherein the extension length is set to be in a range from 120 nm to 150 nm. 
 
     
     
       4. The negative capacitance FinFET device of  claim 3 ,
 wherein the size of the hysteresis window in the negative capacitance FinFET device is from 0.4 V to 0.5 V. 
 
     
     
       5. The negative capacitance FinFET device of  claim 1 ,
 wherein a subthreshold slope (SS) of the negative capacitance FinFET device is from 5 mV/decade to 60 mV/decade at room temperature. 
 
     
     
       6. The negative capacitance FinFET device of  claim 1 ,
 wherein a subthreshold slope (SS) of the negative capacitance FinFET device is from 5 mV/decade to 20 mV/decade at room temperature. 
 
     
     
       7. The negative capacitance FinFET device of  claim 1 ,
 wherein the ferroelectric negative capacitor includes: 
 a substrate; 
 a first electrode layer formed on the substrate; 
 a ferroelectric layer formed on the first electrode layer; and 
 a second electrode layer formed on the ferroelectric layer. 
 
     
     
       8. The negative capacitance FinFET device of  claim 7 ,
 wherein the first electrode layer and the second electrode layer include at least one of lantanium lanthanum strontium manganite (La 0.7 Sr 0.3 MnO 3 ; LSMO), gold (Au), gadolinium scandate (GdScO 3 ), strontium ruthenate (SrRuO 3 ), silicon (Si), polysilicon, copper (Cu), silver (Ag), molybdenum (Mo), nickel (Ni), platinum (Pt), titanium (Ti), tantalum (Ta), and ruthenium (Ru). 
 
     
     
       9. The negative capacitance FinFET device of  claim 7 ,
 wherein the ferroelectric layer includes at least one of PVDF [poly(vinylidenefluoride)], P(VDF-TrFE) [poly (vinylidenefluoride-trifluoroethylene)], PZT (lead zirconate titanate), BTO (barium titanate), BLT (bismuth lanthanum titanate), SBT (strontium bismuth tantalate), SLT (near-stoichiometric lithium tantalate), silicon-doped hafnium oxide (Si-doped HfO 2 ), hafnium zirconium oxide (HfZrO 2 ), and PbZrTiO 3 . 
 
     
     
       10. A manufacturing method of a negative capacitance FinFET device, comprising:
 forming, on a substrate, a FinFET device including a gate stack, a drain electrode and a source electrode; 
 forming a ferroelectric negative capacitor having a negative capacitance; and 
 connecting the ferroelectric negative capacitor to the gate stack of the FinFET device, 
 wherein the FinFET device has an extension length (L ext ) from a side-wall of the gate stack to the drain electrode or the source electrode, and 
 the extension length is set such that a size of a hysteresis window in the negative capacitance FinFET device is in a range from 0.4 V to 1 V or less. 
 
     
     
       11. The manufacturing method of  claim 10 ,
 wherein the extension length is set to be in a range from 80 nm to 150 nm. 
 
     
     
       12. The manufacturing method of  claim 10 ,
 wherein the extension length is set to be in a range from 120 nm to 150 nm. 
 
     
     
       13. The manufacturing method of  claim 12 ,
 wherein the size of the hysteresis window in the negative capacitance FinFET device is from 0.4 V to 0.5 V. 
 
     
     
       14. The manufacturing method of  claim 10 ,
 wherein a subthreshold slope (SS) of the negative capacitance FinFET device is from 5 mV/decade to 60 mV/decade at room temperature. 
 
     
     
       15. The manufacturing method of  claim 10 ,
 wherein a subthreshold slope (SS) of the negative capacitance FinFET device is from 5 mV/decade to 20 mV/decade at room temperature. 
 
     
     
       16. The manufacturing method of  claim 10 ,
 wherein the forming of a ferroelectric negative capacitor includes: 
 forming a substrate; 
 forming a first electrode layer on the substrate; 
 forming a ferroelectric layer on the first electrode layer; and 
 forming a second electrode layer on the ferroelectric layer. 
 
     
     
       17. The manufacturing method of  claim 16 ,
 wherein the first electrode layer and the second electrode layer include at least one of lantanium lanthanum strontium manganite (La 0.7 Sr 0.3 MnO 3 ; LSMO), gold (Au), gadolinium scandate (GdScO 3 ), strontium ruthenate (SrRuO 3 ), silicon (Si), polysilicon, copper (Cu), silver (Ag), molybdenum (Mo), nickel (Ni), platinum (Pt), titanium (Ti), tantalum (Ta), and ruthenium (Ru). 
 
     
     
       18. The manufacturing method of  claim 16 ,
 wherein the ferroelectric layer includes at least one of PVDF [poly(vinylidenefluoride)], P(VDF-TrFE) [poly (vinylidenefluoride-trifluoroethylene)], PZT (lead zirconate titanate), BTO (barium titanate), BLT (bismuth lanthanum titanate), SBT (strontium bismuth tantalate), SLT (near-stoichiometric lithium tantalate), silicon-doped hafnium oxide (Si-doped HfO 2 ), hafnium zirconium oxide (HfZrO 2 ), and PbZrTiO 3 . 
 
     
     
       19. A negative capacitance FinFET device, comprising:
 a ferroelectric negative capacitor;   a gate electrically connected to the ferroelectric negative capacitor;   a source electrode and a drain electrode on opposing sides of the gate, respectively, wherein the gate is spaced apart from the source electrode or the drain electrode by a distance such that a size of a hysteresis window in the negative capacitance FinFET device is in a range from 0.4 V to 1 V; and   a fin extending from the source electrode to the drain electrode.    
     
     
       20. The negative capacitance FinFET device of claim 19, wherein the ferroelectric negative capacitor comprises a first electrode layer, a second electrode layer, and a ferroelectric layer between the first and second electrode layers, and
 wherein the gate is electrically connected to the first electrode layer of the ferroelectric negative capacitor.    
     
     
       21. The negative capacitance FinFET device of claim 20, wherein the first electrode layer and the second electrode layer include at least one of lantanium strontium manganite (La 0.7 Sr 0.3 MnO 3 ; LSMO), gold (Au), gadolinium scandate (GdScO 3 ), strontium ruthenate (SrRuO 3 ), silicon (Si), polysilicon, copper (Cu), silver (Ag), molybdenum (Mo), nickel (Ni), platinum (Pt), titanium (Ti), tantalum (Ta), and ruthenium (Ru).  
     
     
       22. The negative capacitance FinFET device of claim 20, wherein the ferroelectric layer includes at least one of PVDF [poly(vinylidenefluoride)], P(VDF-TrFE) [poly(vinylidenefluoride-trifluoroethylene)], PZT (lead zirconate titanate), BTO (barium titanate), BLT (bismuth lanthanum titanate), SBT (strontium bismuth tantalate), SLT (near-stoichiometric lithium tantalate), silicon-doped hafnium oxide (Si-doped HfO 2 ), hafnium zirconium oxide (HfZrO 2 ), and PbZrTiO 3 .  
     
     
       23. The negative capacitance FinFET device of claim 19, wherein a subthreshold slope (SS) of the negative capacitance FinFET device is from 5 mV/decade to 60 mV/decade at room temperature.  
     
     
       24. The negative capacitance FinFET device of claim 23, wherein the subthreshold slope (SS) of the negative capacitance FinFET device is from 5 mV/decade to 20 mV/decade at room temperature.  
     
     
       25. The negative capacitance FinFET device of claim 19, wherein the fin comprises a plurality of fins that extend from the source electrode to the drain electrode and are spaced apart from each other in a first direction by a first distance, and
 wherein each of the plurality of fins has a first width in the first direction, and a sum of the first distance and the first width is five times the first width.    
     
     
       26. The negative capacitance FinFET device of claim 19, wherein the hysteresis window in the negative capacitance FinFET device is from 0.4 V to 0.5 V.  
     
     
       27. The negative capacitance FinFET device of claim 19, wherein a driving voltage of the negative capacitance FinFET device is 0.5 V or less.  
     
     
       28. A FinFET device, comprising:
 a semiconductor fin having a gate stack thereon, which is capacitively coupled to a ferroelectric layer that provides negative capacitance characteristics to the FinFET device; and   a source electrode and a drain electrode electrically connected to opposing ends of the semiconductor fin on opposing sides of the gate stack, said gate stack having a sidewall spaced apart from the source electrode or the drain electrode by a sufficient distance to yield a hysteresis window within an I D  versus V G  characteristic of the FinFET device, which is in a range from 0.4 V to 1 V, where I D  and V G  correspond to a drain current and a gate voltage in the FinFET device, respectively.    
     
     
       29. The FinFET device of claim 28, wherein the ferroelectric layer includes at least one of PVDF [poly(vinylidenefluoride)], P(VDF-TrFE) [poly(vinylidenefluoride-trifluoroethylene)], PZT (lead zirconate titanate), BTO (barium titanate), BLT (bismuth lanthanum titanate), SBT (strontium bismuth tantalate), SLT (near-stoichiometric lithium tantalate), silicon-doped hafnium oxide (Si-doped HfO 2 ), hafnium zirconium oxide (HfZrO 2 ), and PbZrTiO 3 .  
     
     
       30. The FinFET device of claim 28, wherein a subthreshold slope (SS) of the FinFET device is in a range from 5 mV/decade to 60 mV/decade at room temperature.  
     
     
       31. The FinFET device of claim 30, wherein the subthreshold slope (SS) of the negative capacitance FinFET device is in a range from 5 mV/decade to 20 mV/decade at room temperature.  
     
     
       32. The FinFET device of claim 28, wherein the semiconductor fin is one of a plurality of spaced-apart fins that extend from the source electrode to the drain electrode; and wherein the gate stack extends on the plurality of spaced-apart fins.  
     
     
       33. The FinFET device of claim 28, wherein the hysteresis window in the FinFET device is from 0.4 V to 0.5 V; wherein the gate stack comprises an oxide layer on the semiconductor fin; and wherein a capacitor associated with the oxide layer and a capacitor associated with the ferroelectric layer are electrically coupled in series.  
     
     
       34. The FinFET device of claim 28, wherein a driving voltage of the FinFET device is 0.5 V or less; and wherein the sidewall of the gate stack is spaced from the source electrode or the drain electrode by an extension length (Lext) in a range from 80 nm to 150 nm.